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bjt, jfet, vbic, dio: allow plotting of small signal parameter like charges, capacitances and conductances in dc sweeps

pre-master-46
dwarning 9 years ago
committed by rlar
parent
commit
14fc59b83d
  1. 2
      src/spicelib/devices/bjt/bjtload.c
  2. 2
      src/spicelib/devices/dio/dioload.c
  3. 2
      src/spicelib/devices/jfet/jfetload.c
  4. 2
      src/spicelib/devices/vbic/vbicload.c

2
src/spicelib/devices/bjt/bjtload.c

@ -534,7 +534,7 @@ next1: vtn=vt*here->BJTtemissionCoeffF;
gmu=gbc/here->BJTtBetaR+gbcn;
go=(gbc+(cex-cbc)*dqbdvc/qb)/qb;
gm=(gex-(cex-cbc)*dqbdve/qb)/qb-go;
if( (ckt->CKTmode & (MODETRAN | MODEAC)) ||
if( (ckt->CKTmode & (MODEDCTRANCURVE | MODETRAN | MODEAC)) ||
((ckt->CKTmode & MODETRANOP) && (ckt->CKTmode & MODEUIC)) ||
(ckt->CKTmode & MODEINITSMSIG)) {
/*

2
src/spicelib/devices/dio/dioload.c

@ -300,7 +300,7 @@ next1: if (model->DIOsatSWCurGiven) { /* sidewall current */
}
if ((ckt->CKTmode & (MODETRAN | MODEAC | MODEINITSMSIG)) ||
if ((ckt->CKTmode & (MODEDCTRANCURVE | MODETRAN | MODEAC | MODEINITSMSIG)) ||
((ckt->CKTmode & MODETRANOP) && (ckt->CKTmode & MODEUIC))) {
/*
* charge storage elements

2
src/spicelib/devices/jfet/jfetload.c

@ -400,7 +400,7 @@ JFETload(GENmodel *inModel, CKTcircuit *ckt)
* compute equivalent drain current source
*/
cd=cdrain-cgd;
if ( (ckt->CKTmode & (MODETRAN | MODEAC | MODEINITSMSIG) ) ||
if ( (ckt->CKTmode & (MODEDCTRANCURVE | MODETRAN | MODEAC | MODEINITSMSIG) ) ||
((ckt->CKTmode & MODETRANOP) && (ckt->CKTmode & MODEUIC)) ){
/*
* charge storage elements

2
src/spicelib/devices/vbic/vbicload.c

@ -786,7 +786,7 @@ next1:
Ibcp += ckt->CKTgmin*Vbcp;
Ibcp_Vbcp += ckt->CKTgmin;
if( (ckt->CKTmode & (MODETRAN | MODEAC)) ||
if( (ckt->CKTmode & (MODEDCTRANCURVE | MODETRAN | MODEAC)) ||
((ckt->CKTmode & MODETRANOP) && (ckt->CKTmode & MODEUIC)) ||
(ckt->CKTmode & MODEINITSMSIG)) {
/*

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