XSPICE example: delta-sigma converter

examples/xspice/delta-sigma/README

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+A simple delta sigma converter using XSPICE
+according to 
+Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005
+Fig. 2.13, p. 31; Fig. 2.27, p.58
+
+
+delta-sigma-1.cir
+converter complete, tested against sine input
+
+mod1-ct.cir
+first order modulator
+consists of analog continuous time integrator and
+digitally latched comparator
+
+count-latch-dac.cir
+contains subcircuits of 
+10 bit digital latch
+10 bit counter, non-revolving, saturating
+simple 10 bit DAC with analog B source
+
+mod1-ct-test.cir
+test of modulator with sine input, shows noise shaping 20dB/decade
+
+counter-test.cir
+simple test with reset

examples/xspice/delta-sigma/count-latch-dac.cir

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+* counter, latch DAC
+
+* 10 bit synchronous digital counter
+* inhibit at overflow, no revolving
+.subckt count10 din dinb dclk drs dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 
+
+* j k clk set reset out nout
+ajk1 din dinb diclk ds1 drs dout1 dnout1 jkflop
+ajk2 dout1 dout1 diclk ds2 drs dout2 dnout2 jkflop
+ajk3 djk3 djk3 diclk ds3 drs dout3 dnout3 jkflop
+ajk4 djk4 djk4 diclk ds4 drs dout4 dnout4 jkflop
+ajk5 djk5 djk5 diclk ds1 drs dout5 dnout5 jkflop
+ajk6 djk6 djk6 diclk ds2 drs dout6 dnout6 jkflop
+ajk7 djk7 djk7 diclk ds3 drs dout7 dnout8 jkflop
+ajk8 djk8 djk8 diclk ds4 drs dout8 dnout8 jkflop
+ajk9 djk9 djk9 diclk ds3 drs dout9 dnout9 jkflop
+ajk10 djk10 djk10 diclk ds4 drs dout10 dnout10 jkflop
+
+aand1 [dout1 dout2] djk3 and1
+aand2 [dout1 dout2 dout3] djk4 and1
+aand3 [dout1 dout2 dout3 dout4] djk5 and1
+aand4 [dout1 dout2 dout3 dout4 dout5] djk6 and1
+aand5 [dout1 dout2 dout3 dout4 dout5 dout6] djk7 and1
+aand6 [dout1 dout2 dout3 dout4 dout5 dout6 dout7] djk8 and1
+aand7 [dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8] djk9 and1
+aand8 [dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9] djk10 and1
+
+* inhibit revolving of counter, just let it saturate
+* (footnote p. 57)
+aand_all [dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10] dinhibit nand1
+aandclk [dclk dinhibit] diclk and1
+
+
+.model nand1 d_nand(rise_delay = 1e-9 fall_delay = 1e-9
++ input_load = 0.5e-12)
+
+.model and1 d_and(rise_delay = 1e-9 fall_delay = 1e-9
++ input_load = 0.5e-12)
+
+.model jkflop d_jkff(clk_delay = 1.0e-9 set_delay = 1e-9
++ reset_delay = 1e-9 ic = 0 rise_delay = 1.0e-9
++ fall_delay = 1e-9)
+
+.ends count 10
+
+** 10 bit edge triggered latch
+.subckt latch10 din1 din2 din3 din4 din5 din6 din7 din8 din9 din10
++ dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 dclk
+
+*data clk set reset out nout
+aff1 din1 dclk dzero dzero dout1 dnout1 flop1
+aff2 din2 dclk dzero dzero dout2 dnout2 flop1
+aff3 din3 dclk dzero dzero dout3 dnout3 flop1
+aff4 din4 dclk dzero dzero dout4 dnout4 flop1
+aff5 din5 dclk dzero dzero dout5 dnout5 flop1
+aff6 din6 dclk dzero dzero dout6 dnout6 flop1
+aff7 din7 dclk dzero dzero dout7 dnout7 flop1
+aff8 din8 dclk dzero dzero dout8 dnout8 flop1
+aff9 din9 dclk dzero dzero dout9 dnout9 flop1
+aff10 din10 dclk dzero dzero dout10 dnout10 flop1
+
+.model flop1 d_dff(clk_delay = 1e-9 set_delay = 0
++ reset_delay = 0 ic = 0 rise_delay = 1e-9
++ fall_delay = 1e-9)
+
+.ends latch10
+
+** emulation of 10 bit DAC
+.subckt dac10  din1 din2 din3 din4 din5 din6 din7 din8 din9 din10 aout
+.param vref=1
+abridge1 [din1 din2 din3 din4 din5 din6 din7 din8 din9 din10] 
++ [ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10] dac1
+BVout aout 0 V = 'vref'*(v(ain10)/2 + v(ain9)/4 + v(ain8)/8 + v(ain7)/16 + v(ain6)/32 +
++ v(ain5)/64 + v(ain4)/128 + v(ain3)/256 + v(ain2)/512 + v(ain1)/1024)
+
+.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
++ input_load = 5.0e-12 t_rise = 1e-9
++ t_fall = 1e-9)
+
+.ends dac10
+

examples/xspice/delta-sigma/counter-test.cir

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+* 10 bit synchronous digital counter
+* inhibit at overflow, no revolving
+* according to Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005
+* Fig. 2.27, p. 58
+
+* clock generation
+* PULSE(V1 V2 TD TR TF PW PER)
+vclk aclk 0 dc 0 pulse(0 1 1u 2n 2n 1u 2u)
+
+* reset generation
+* single pulse, actual value stored in latch and read by DAC
+vres ars 0 dc 0 pulse(0 1 1.1m 2n 2n 1u 2.2m)
+
+vone aone 0 dc 1
+vzero azero 0 dc 0
+
+* digital one
+* digital zero
+abridge1 [aone azero] [done dzero] adc_buff
+.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
+
+* digital clock
+* digital reset
+abridge2 [aclk ars] [dclk dreset] adc_buff
+.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
+
+XCounter done done dclk dreset dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 count10
+Xlatch dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10
++ dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 dreset
++ latch10
+Xdac dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 adacout dac10 
+
+.include count-latch-dac.cir
+
+.control
+tran 1u 2.5m
+eprint dout1 dout2 dout3 dout4  dout5 dout6 dout7 dout8 dout9 dout10 > digi4b.txt
+eprint dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 >> digi4b.txt
+plot adacout
+.endc
+
+.end

examples/xspice/delta-sigma/delta-sigma-1.cir

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+* delta sigma A/D converter 9 bit
+* first-order continuous time delta sigma modulator
+* sinc filter with counter
+* according to Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005
+* Fig. 2.13, p. 31; Fig. 2.27, p.58
+
+** sine input signal parameters
+.param infreq=500 inampl=0.5
+** clock
+.param clkfreq=5Meg
+** simulation time
+.param simtime = 2m
+.csparam simtime = 'simtime'
+** sample clock cycles
+.param samples=500
+
+.global dzero done
+
+** input signal
+* SIN(VO VA FREQ TD THETA)
+vin inp inm dc 0 sin(0 'inampl' 'infreq' 0 0)
+* steps from -0.5 to 0.4
+*vin inp inm dc 0 pwl(0 -0.5 0.2m -0.5 0.201m -0.4 0.4m -0.4 0.401m -0.3 0.6m -0.3
+*+  0.601m -0.2 0.8m -0.2  0.801m -0.1 1.0m -0.1  1.001m 0.0 1.2m 0.0  1.201m 0.1 1.4m 0.1 
+*+  1.401m 0.2 1.6m 0.2 1.601m 0.3 1.8m 0.3 1.801m 0.4 2m 0.4)
+
+** clock and constant logic levels
+* PULSE(V1 V2 TD TR TF PW PER)
+vclk aclk 0 dc 0 pulse(0 1 0.1u 2n 2n '1/clkfreq/2' '1/clkfreq')
+
+* digital one
+* digital zero
+vone aone 0 dc 1
+vzero azero 0 dc 0
+abridge1 [aone azero] [done dzero] adc_buff
+.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
+
+* digital clock
+abridge2 [aclk] [dclk] adc_buff
+.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
+
+****** delta-sigma converter****************************************************************
+* modulator
+* inp inm: analog in + -
+* dclk digital clock in
+* dv, dvb: modulator non-inverting/inverting out
+Xmod inp inm dclk dv dvb mod1
+* sinc filter, decimator
+* dlout1 ..dlout10: converter 10 bit digital out
+xsinc dv dvb dclk  dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 sinc1
+********************************************************************************************
+
+** DACs for measuring and plotting
+* converter output
+Xdac_latch dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 adaclout dac10 
+* counter inside of sinc filter
+Xdac_counter xsinc.dout1 xsinc.dout2 xsinc.dout3 xsinc.dout4 xsinc.dout5
++ xsinc.dout6 xsinc.dout7 xsinc.dout8 xsinc.dout9 xsinc.dout10 adaccout dac10
+
+* load modulator mod1 subcircuit
+.include mod1-ct.cir
+
+* load counter, d-latch and 10 bit DAC
+.include count-latch-dac.cir
+
+** sinc filter 1st order subcircuit
+.subckt sinc1 din dinb dclk dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10
+XCounter din dinb dclk ddivndel2 dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 count10
+Xlatch dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10
++ dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 ddivndel1
++ latch10
+
+* digital divider dclk/samples
+adivn dclk ddivn divider
+.model divider d_fdiv(div_factor = 'samples' high_cycles = 1
++ i_count = 0 rise_delay = 1e-9 fall_delay = 1e-9)
+
+* clock delays
+adelay ddivn ddivndel1 buff1 ; set latch
+adelay2 ddivndel1 ddivndel2 buff1 ; reset counter
+.model buff1 d_buffer(rise_delay = '1/clkfreq/8' fall_delay = '1/clkfreq/8'
++ input_load = 0.5e-12)
+
+.ends sinc1
+
+** for plotting
+abridge22 [dclk xsinc.ddivndel1 xsinc.ddivndel2 dv] [acclk acset acres acin] dac1
+.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5
++ input_load = 5.0e-12 t_rise = 1e-9
++ t_fall = 1e-9)
+
+
+.control
+save inp inm adaclout adaccout ; save memory space
+tran 0.1u $&simtime
+* analog out, scaled 'manually'; sinc filter counter; analog differential in
+plot 4.1*(adaclout-0.486) adaccout v(inp)-v(inm) ylimit -0.6 0.6
+* modulator dig out
+* eprint dv > digi1.txt
+* 
+*eprint dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 
+*+ xsinc.dout1 xsinc.dout2 xsinc.dout3 xsinc.dout4 xsinc.dout5
+*+ xsinc.dout6 xsinc.dout7 xsinc.dout8 xsinc.dout9 xsinc.dout10 > digi4b.txt
+.endc
+
+.end

examples/xspice/delta-sigma/mod1-ct-test.cir

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+* first-order delta sigma modulator
+* continuous time
+* according to Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005
+* Fig. 2.13, p. 31
+
+** signal
+.param infreq=13k inampl=0.3
+** clock
+.param clkfreq=5Meg
+** simulation time
+.param simtime = 5m
+.csparam simtime = 'simtime'
+
+** input signal
+*SIN(VO VA FREQ TD THETA)
+vin in+ in- dc 0 sin(0 'inampl' 'infreq' 0 0)
+
+* clock generation
+* PULSE(V1 V2 TD TR TF PW PER)
+vclk aclk 0 dc 0 pulse(0 1 0.1u 2n 2n '1/clkfreq/2' '1/clkfreq')
+
+* digital one
+* digital zero
+vone aone 0 dc 1
+vzero azero 0 dc 0
+abridge1 [aone azero] [done dzero] adc_buff
+.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
+
+* digital clock
+abridge2 [aclk] [dclk] adc_buff
+.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5)
+
+Xmod in+ in- dclk dv dvb mod1
+
+* load mod1 subcircuit
+.include mod1-ct.cir
+
+.control
+save xmod.adffq in+ in- xmod.outintp xmod.outintn
+tran 0.01u $&simtime
+* digit density vs input
+plot xmod.adffq "v(in+) - v(in-)" xlimit 0.1m 0.2m
+* modulator integrator out, digital out
+plot xmod.outintp-xmod.outintn xmod.adffq xlimit 0.140m 0.148m
+*eprint dv dclk > digi1.txt
+linearize xmod.adffq
+fft xmod.adffq
+* noise shaping 20dB/decade
+plot db(xmod.adffq) xlimit 10k 1Meg xlog ylimit -20 -120
+.endc
+
+.end

examples/xspice/delta-sigma/mod1-ct.cir

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+* delta sigma modulator 
+* first order, continuous time
+
+.subckt mod1 ainp ainn dclk ddffq ddffqb
+* integrator and summer
+Ri1 ainn inintn 500
+Rf1 adffq inintn 500
+Cint1 outintp inintn 1n
+.IC v(outintp) = 0 v(inintp) = 0
+*
+Rshunt1 outintp 0 100Meg
+Rshunt2 initn 0 100Meg
+*
+Ri2 ainp inintp 500
+Rf2 adffqb inintp 500
+Cint2 outintn inintp 1n
+.IC v(outintn) = 0 v(inintn) = 0
+*
+Rshunt3 outintn 0 100Meg
+Rshunt4 inintp 0 100Meg
+*
+aint %vd(inintp inintn) %vd(outintp outintn) amp
+.model amp gain ( in_offset =0.0 gain =100000
++ out_offset = 0)
+
+* latched comparator (code model or B source, analog in, digital out)
+*acomp %vd(outintp outintn) acompout limit5
+*.model limit5 limit(in_offset=0 gain=100000 out_lower_limit=-1.0
+*+ out_upper_limit=1.0 limit_range=0.10 fraction=FALSE)
+*
+BComp acompout 0 V = (V(outintp) - V(outintn)) >= 0 ? 1 : -1
+*
+abridge2 [acompout] [dcompout] adc_buff
+.model adc_buff adc_bridge(in_low = 0 in_high = 0)
+*
+* D flip flop: data clk set reset out nout
+adff1 dcompout dclk ds drs ddffq ddffqb flop2
+.model flop2 d_dff(clk_delay = 1e-9 set_delay = 1.0e-9
++ reset_delay = 1.0e-9 ic = 0 rise_delay = 1.0e-9
++ fall_delay = 1e-9)
+
+abridge1 [ddffq ddffqb dclk] [adffq adffqb aclk] dac1
+.model dac1 dac_bridge(out_low = -1 out_high = 1 out_undef = 0
++ input_load = 5.0e-12
+
+.ends mod1