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various digital simulations of a 4-bit NAND gate full adder:
various digital simulations of a 4-bit NAND gate full adder:
Bipolar, MOS, behavioral, and event basedpre-master-46
Holger Vogt
8 years ago
7 changed files with 579 additions and 0 deletions
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226examples/digital/74HCng_short_2.lib
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23examples/digital/adder-comparison.txt
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84examples/digital/adder_Xspice.cir
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69examples/digital/adder_behav.cir
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88examples/digital/adder_bip.cir
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79examples/digital/adder_mos.cir
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10examples/digital/nggtk.tcl
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* 74hcng.lib |
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* |
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* derived from 74HCxxx Model libraray for LTSPICE from www.linear.com/software |
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* |
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* Revision 1.01 06/25/2018 test devices NAND, NOR, and XOR as XSPICE subcircuit for ngspice |
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* |
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* All parts have been divided into three sections. |
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* |
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* >--| A-D-Converter (threshold VCC1/2) |----| Event LOGIC Axx (delay) |----| OUTPUT LEVEL D-A (rise and fall times) |--> |
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* |
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* Delays are given for Vcc = 2V/4.5V/6V (HC) from the |
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* Philips data sheets. http://www.philipslogic.com |
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* |
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* Delays are given for Vcc = 2V/4.5V/6V . |
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* Used delay: Td = (Tpd-Tr/2)*(4.5-0.5)/(Vcc-0.5) |
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* The gate delay has to be set to tpd minus 3ns for the input filter |
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* and another minus 3ns for Trise/2 |
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* td1 = tpd - 3ns - 3ns |
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* |
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.param vcc=5 tripdt=6n |
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*********************************************************************************** |
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* The 74HCXX gates |
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* |
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* 2-input NAND gate |
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* vcc 2 /4.5/5 /6 |
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* tpd 25n/9n/7n/7n |
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* tr 19n/7n / /6n |
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.SUBCKT 74HC00 in1 in2 out NVCC NVGND vcc1={vcc} tripdt1={tripdt} |
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.param td1={1e-9*(9-3-3)*4.0/(vcc1-0.5)} |
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.param Rout={60*4.0/(vcc1-0.5)} $ standard output driver |
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*Cin1 in1 0 3.5p |
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*Cin2 in2 0 3.5p |
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abridge2 [in1 in2] [din1 din2] adc_buff |
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.model adc_buff adc_bridge(in_low = {vcc1/2.0} in_high = {vcc1/2.0}) |
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a6 [din1 din2] dout nand1 |
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.model nand1 d_nand(rise_delay = {td1} fall_delay = {td1} |
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+ input_load = 0.5e-12) |
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abridge1 [dout] [out20] dac1 |
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.model dac1 dac_bridge(out_low = 0.0 out_high = {vcc1} out_undef = {vcc1/2.0} |
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+ input_load = 5.0e-12 t_rise = {tripdt1} |
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+ t_fall = {tripdt1}) |
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Rout out20 out {Rout} |
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.ends |
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* 2-input NOR gate |
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* tpd 25n/9n/7n |
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* tr 19n/7n/6n |
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.SUBCKT 74HC02 in1 in2 out NVCC NVGND vcc1={vcc} tripdt1={tripdt} |
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.param td1={1e-9*(9-3-3)*4.0/(vcc1-0.5)} |
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.param Rout={60*4.0/(vcc1-0.5)} $ standard output driver |
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*Cin1 in1 0 3.5p |
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*Cin2 in2 0 3.5p |
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abridge2 [in1 in2] [din1 din2] adc_buff |
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.model adc_buff adc_bridge(in_low = {vcc1/2.0} in_high = {vcc1/2.0}) |
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a6 [din1 din2] dout nor1 |
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.model nor1 d_nor(rise_delay = {td1} fall_delay = {td1} input_load = 0.5e-12) |
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abridge1 [dout] [out20] dac1 |
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.model dac1 dac_bridge(out_low = 0.0 out_high = {vcc1} out_undef = {vcc1/2.0} |
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+ input_load = 5.0e-12 t_rise = {tripdt1} t_fall = {tripdt1}) |
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Rout out20 out {Rout} |
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.ends |
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** 2-input AND gate |
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* tpd 25n/9n/7n |
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* tr 19n/7n/6n |
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.SUBCKT 74HC08 in1 in2 out NVCC NVGND vcc1={vcc} tripdt1={tripdt} |
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.param td1={1e-9*(9-3-3)*4.0/(vcc1-0.5)} |
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.param Rout={60*4.0/(vcc1-0.5)} $ standard output driver |
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*Cin1 in1 0 3.5p |
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*Cin2 in2 0 3.5p |
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abridge2 [in1 in2] [din1 din2] adc_buff |
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.model adc_buff adc_bridge(in_low = {vcc1/2.0} in_high = {vcc1/2.0}) |
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a6 [din1 din2] dout and1 |
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.model and1 d_and(rise_delay = {td1} fall_delay = {td1} |
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+ input_load = 0.5e-12) |
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abridge1 [dout] [out20] dac1 |
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.model dac1 dac_bridge(out_low = 0.0 out_high = {vcc1} out_undef = {vcc1/2.0} |
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+ input_load = 5.0e-12 t_rise = {tripdt1} |
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+ t_fall = {tripdt1}) |
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Rout out20 out {Rout} |
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.ends |
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** |
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* 2-input OR gate |
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* tpd 25n/9n/7n |
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* tr 19n/7n/6n |
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.SUBCKT 74HC32 in1 in2 out NVCC NVGND vcc1={vcc} tripdt1={tripdt} |
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.param td1={1e-9*(9-3-3)*4.0/(vcc1-0.5)} |
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.param Rout={60*4.0/(vcc1-0.5)} $ standard output driver |
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*Cin1 in1 0 3.5p |
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*Cin2 in2 0 3.5p |
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abridge2 [in1 in2] [din1 din2] adc_buff |
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.model adc_buff adc_bridge(in_low = {vcc1/2.0} in_high = {vcc1/2.0}) |
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a6 [din1 din2] dout or1 |
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.model or1 d_or(rise_delay = {td1} fall_delay = {td1} input_load = 0.5e-12) |
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abridge1 [dout] [out20] dac1 |
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.model dac1 dac_bridge(out_low = 0.0 out_high = {vcc1} out_undef = {vcc1/2.0} |
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+ input_load = 5.0e-12 t_rise = {tripdt1} t_fall = {tripdt1}) |
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Rout out20 out {Rout} |
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.ends |
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* 2-input EXOR gate |
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* tpd 39n/14n/11n |
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* tr 19n/7n/6n |
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.SUBCKT 74HC86 in1 in2 out NVCC NVGND vcc1={vcc} tripdt1={tripdt} |
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.param td1={1e-9*(14-3-3)*4.0/(vcc1-0.5)} |
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.param Rout={60*4.0/(vcc1-0.5)} $ standard output driver |
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*Cin1 in1 0 3.5p |
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*Cin2 in2 0 3.5p |
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abridge2 [in1 in2] [din1 din2] adc_buff |
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.model adc_buff adc_bridge(in_low = {vcc1/2.0} in_high = {vcc1/2.0}) |
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a6 [din1 din2] dout xor3 |
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.model xor3 d_xor(rise_delay = {td1} fall_delay = {td1} |
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+ input_load = 0.5e-12) |
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abridge1 [dout] [out20] dac1 |
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.model dac1 dac_bridge(out_low = 0.0 out_high = {vcc1} out_undef = {vcc1/2.0} |
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+ input_load = 5.0e-12 t_rise = {tripdt1} t_fall = {tripdt1}) |
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Rout out20 out {Rout} |
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.ends |
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* |
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*============================================================================ |
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* |
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* A hopefully real transistor level based model of the 74HCU04. The model |
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* comes directly from philips. http://www.philipslogic.com/support/spice/ |
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* This a unbuffered inverter which is often used in LC or crystal oscillators. |
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* Inverter, unbuffered |
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* Original Philips model used. |
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.SUBCKT 74HCU04 A Y VCC VGND vcc1={vcc} speed1={speed} tripdt1={tripdt} |
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*Rin A A1 200 |
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*Cin A1 VGND 3p |
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*XAY A1 Y VCC VGND 74HC04_INV0 |
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XAY A Y VCC VGND 74HC04_INV0 |
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.ends |
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* |
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* |
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.SUBCKT 74HC04_INV0 2 3 80 90 |
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*IN=2, OUT=3, VCC=80, GND=90 |
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XINP 20 25 50 60 74HC_INP0N |
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XOUTP 25 30 50 60 74HC_OUTPN |
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L1 80 50 6.87NH |
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L2 60 90 6.87NH |
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L3 2 20 5.97NH |
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L4 30 3 5.97NH |
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C1 50 90 1.5P |
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C2 60 90 1.5P |
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C3 20 90 1.5P |
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C4 3 90 1.5P |
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.ENDS |
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* |
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.SUBCKT 74HC_INP0N 2 3 50 60 |
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*IN=2, OUT=3, VCC=50, GND=60 |
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R1 2 3 100 |
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MP1 3 50 50 50 MHCPEN W=20U L=2.4U AD=100P AS=100P PD=40U PS= 20U |
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MN1 3 60 60 60 MHCNEN W=35U L=2.4U AD=260P AS=260P PD=70U PS= 20U |
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.ENDS |
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* |
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.SUBCKT 74HC_OUTPN 2 3 50 60 |
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*IN=2, OUT=3, VCC=50, GND=60 |
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R1 2 4 100 |
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MP1 3 4 50 50 MHCPEN W=360U L=2.4U AD=400P AS=400P PD=10U PS=180U |
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MN1 3 4 60 60 MHCNEN W=140U L=2.4U AD=200P AS=300P PD=10U PS=130U |
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R2 4 5 50 |
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MP2 3 5 50 50 MHCPEN W=360U L=2.4U AD=400P AS=400P PD=10U PS=180U |
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MN2 3 5 60 60 MHCNEN W=140U L=2.4U AD=200P AS=200P PD=10U PS=130U |
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R3 5 6 50 |
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MP3 3 6 50 50 MHCPEN W=360U L=2.4U AD=400P AS=400P PD=10U PS=180U |
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MN3 3 6 60 60 MHCNEN W=140U L=2.4U AD=200P AS=200P PD=10U PS=130U |
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.ENDS |
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************************************************ |
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* NOMINAL N-Channel Transistor * |
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* UCB-3 Parameter Set * |
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* HIGH-SPEED CMOS Logic Family * |
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* 10-Jan.-1995 * |
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************************************************ |
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.Model MHCNEN NMOS ( |
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+LEVEL = 3 |
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+KP = 45.3E-6 |
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+VTO = 0.72 |
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+TOX = 51.5E-9 |
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+NSUB = 2.8E15 |
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+GAMMA = 0.94 |
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+PHI = 0.65 |
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+VMAX = 150E3 |
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+RS = 40 |
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+RD = 40 |
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+XJ = 0.11E-6 |
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+LD = 0.52E-6 |
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+DELTA = 0.315 |
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+THETA = 0.054 |
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+ETA = 0.025 |
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+KAPPA = 0.0 |
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+WD = 0.0 ) |
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*********************************************** |
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* NOMINAL P-Channel transistor * |
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* UCB-3 Parameter Set * |
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* HIGH-SPEED CMOS Logic Family * |
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* 10-Jan.-1995 * |
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*********************************************** |
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.Model MHCPEN PMOS ( |
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+LEVEL = 3 |
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+KP = 22.1E-6 |
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+VTO = -0.71 |
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+TOX = 51.5E-9 |
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+NSUB = 3.3E16 |
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+GAMMA = 0.92 |
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+PHI = 0.65 |
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+VMAX = 970E3 |
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+RS = 80 |
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+RD = 80 |
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+XJ = 0.63E-6 |
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+LD = 0.23E-6 |
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+DELTA = 2.24 |
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+THETA = 0.108 |
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+ETA = 0.322 |
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+KAPPA = 0.0 |
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+WD = 0.0 ) |
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@ -0,0 +1,23 @@ |
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Compare four different 4-bit full adders, |
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made of NAND gates |
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Simulating for 6400ns |
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adder_bib |
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The old spice bipolar NAND gate full adder |
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Simulation time 14.0s |
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adder_mos |
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A MOS NAND gate inverter, using BSIM3 and OpenMP |
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Simulation time 10.5s |
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adder_behav |
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NAND gates made with XSPICE digital devices, |
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but each has an analog interface, the interconnect |
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is analog, gate library is 74HCng_short_2.lib |
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Simulation time 1.9s |
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adder_Xspice |
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Fully digital, event node based NAND gates |
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digital plotting into vcd file, display with gtkwave |
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Simulation time 0.27s |
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@ -0,0 +1,84 @@ |
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ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER |
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*** SUBCIRCUIT DEFINITIONS |
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.SUBCKT NAND in1 in2 out |
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* NODES: INPUT(2), OUTPUT |
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a6 [in1 in2] out nand1 |
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.ENDS NAND |
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.model nand1 d_nand(rise_delay = 0.7e-9 fall_delay = 0.7e-9 |
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+ input_load = 0.5e-12) |
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.SUBCKT ONEBIT 1 2 3 4 5 |
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* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT |
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X1 1 2 7 NAND |
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X2 1 7 8 NAND |
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X3 2 7 9 NAND |
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X4 8 9 10 NAND |
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X5 3 10 11 NAND |
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X6 3 11 12 NAND |
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X7 10 11 13 NAND |
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X8 12 13 4 NAND |
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X9 11 7 5 NAND |
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.ENDS ONEBIT |
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.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 |
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* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, |
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* CARRY-IN, CARRY-OUT |
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X1 1 2 7 5 10 ONEBIT |
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X2 3 4 10 6 8 ONEBIT |
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.ENDS TWOBIT |
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.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 |
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* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), |
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* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT |
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X1 1 2 3 4 9 10 13 16 TWOBIT |
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X2 5 6 7 8 11 12 16 14 TWOBIT |
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.ENDS FOURBIT |
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*** ALL INPUTS (analog) |
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VIN1A a1 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 20NS 50NS) |
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VIN1B a2 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 30NS 100NS) |
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VIN2A a3 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 50NS 200NS) |
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VIN2B a4 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 90NS 400NS) |
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VIN3A a5 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 170NS 800NS) |
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VIN3B a6 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 330NS 1600NS) |
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VIN4A a7 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 650NS 3200NS) |
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VIN4B a8 0 DC 0 PULSE(0 3 0 0.5NS 0.5NS 1290NS 6400NS) |
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*** analog to digital |
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abridge2 [a1 a2 a3 a4 a5 a6 a7 a8] [1 2 3 4 5 6 7 8] adc_buff |
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.model adc_buff adc_bridge(in_low = 1 in_high = 2) |
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*** digital 0 |
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V0 a0 0 0 |
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abridge0 [a0] [d0] adc_buff |
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*** DEFINE NOMINAL CIRCUIT |
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X1 1 2 3 4 5 6 7 8 s0 s1 s2 s3 d0 c3 FOURBIT |
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*.TRAN 500p 6400NS |
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* save inputs |
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*.save V(a1) V(a2) V(a3) V(a4) V(a5) V(a6) V(a7) V(a8) |
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*.save v(1) |
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.control |
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*save v(1) |
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TRAN 500p 6400NS |
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rusage |
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display |
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edisplay |
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* save data to input directory |
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cd $inputdir |
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eprvcd 1 2 3 4 5 6 7 8 s0 s1 s2 s3 c3 > adder_x.vcd |
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* plotting the vcd file (e.g. with GTKWave) |
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* For Windows: returns control to ngspice |
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shell start gtkwave adder_x.vcd --script nggtk.tcl |
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* Others |
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*shell gtkwave adder_x.vcd --script nggtk.tcl & |
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.endc |
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.END |
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@ -0,0 +1,69 @@ |
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ADDER - 4 BIT ALL-74HC00-GATE BINARY ADDER |
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* behavioral gate description |
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*** SUBCIRCUIT DEFINITIONS |
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.include D:\Spice_general\ngspice\examples\digital\74HCng_short_2.lib |
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.param vcc=3 tripdt=6n |
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.SUBCKT ONEBIT 1 2 3 4 5 6 |
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* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC |
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X1 1 2 7 6 0 74HC00 |
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X2 1 7 8 6 0 74HC00 |
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X3 2 7 9 6 0 74HC00 |
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X4 8 9 10 6 0 74HC00 |
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X5 3 10 11 6 0 74HC00 |
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X6 3 11 12 6 0 74HC00 |
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X7 10 11 13 6 0 74HC00 |
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X8 12 13 4 6 0 74HC00 |
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X9 11 7 5 6 0 74HC00 |
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.ENDS ONEBIT |
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.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 |
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* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, |
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* CARRY-IN, CARRY-OUT, VCC |
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X1 1 2 7 5 10 9 ONEBIT |
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X2 3 4 10 6 8 9 ONEBIT |
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.ENDS TWOBIT |
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.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
||||
|
* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), |
||||
|
* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC |
||||
|
X1 1 2 3 4 9 10 13 16 15 TWOBIT |
||||
|
X2 5 6 7 8 11 12 16 14 15 TWOBIT |
||||
|
.ENDS FOURBIT |
||||
|
|
||||
|
*** POWER |
||||
|
VCC 99 0 DC 3.3V |
||||
|
|
||||
|
*** ALL INPUTS |
||||
|
VIN1A 1 0 DC 0 PULSE(0 3 0 5NS 5NS 20NS 50NS) |
||||
|
VIN1B 2 0 DC 0 PULSE(0 3 0 5NS 5NS 30NS 100NS) |
||||
|
VIN2A 3 0 DC 0 PULSE(0 3 0 5NS 5NS 50NS 200NS) |
||||
|
VIN2B 4 0 DC 0 PULSE(0 3 0 5NS 5NS 90NS 400NS) |
||||
|
VIN3A 5 0 DC 0 PULSE(0 3 0 5NS 5NS 170NS 800NS) |
||||
|
VIN3B 6 0 DC 0 PULSE(0 3 0 5NS 5NS 330NS 1600NS) |
||||
|
VIN4A 7 0 DC 0 PULSE(0 3 0 5NS 5NS 650NS 3200NS) |
||||
|
VIN4B 8 0 DC 0 PULSE(0 3 0 5NS 5NS 1290NS 6400NS) |
||||
|
|
||||
|
*** DEFINE NOMINAL CIRCUIT |
||||
|
X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT |
||||
|
|
||||
|
.option noinit acct |
||||
|
.TRAN 500p 6400NS |
||||
|
* save inputs |
||||
|
.save V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8) |
||||
|
|
||||
|
.control |
||||
|
pre_set strict_errorhandling |
||||
|
unset ngdebug |
||||
|
*save outputs and specials |
||||
|
save x1.x1.x1.7 V(9) V(10) V(11) V(12) V(13) |
||||
|
run |
||||
|
rusage |
||||
|
* plot the inputs, use offset to plot on top of each other |
||||
|
plot v(1) v(2)+4 v(3)+8 v(4)+12 v(5)+16 v(6)+20 v(7)+24 v(8)+28 |
||||
|
* plot the outputs, use offset to plot on top of each other |
||||
|
plot v(9) v(10)+4 v(11)+8 v(12)+12 v(13)+16 |
||||
|
.endc |
||||
|
|
||||
|
.END |
||||
@ -0,0 +1,88 @@ |
|||||
|
ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER |
||||
|
|
||||
|
*** SUBCIRCUIT DEFINITIONS |
||||
|
.SUBCKT NAND 1 2 3 4 |
||||
|
* NODES: INPUT(2), OUTPUT, VCC |
||||
|
Q1 9 5 1 QMOD |
||||
|
D1CLAMP 0 1 DMOD |
||||
|
Q2 9 5 2 QMOD |
||||
|
D2CLAMP 0 2 DMOD |
||||
|
RB 4 5 4K |
||||
|
R1 4 6 1.6K |
||||
|
Q3 6 9 8 QMOD |
||||
|
R2 8 0 1K |
||||
|
RC 4 7 130 |
||||
|
Q4 7 6 10 QMOD |
||||
|
DVBEDROP 10 3 DMOD |
||||
|
Q5 3 8 0 QMOD |
||||
|
.ENDS NAND |
||||
|
|
||||
|
.SUBCKT ONEBIT 1 2 3 4 5 6 |
||||
|
* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC |
||||
|
X1 1 2 7 6 NAND |
||||
|
X2 1 7 8 6 NAND |
||||
|
X3 2 7 9 6 NAND |
||||
|
X4 8 9 10 6 NAND |
||||
|
X5 3 10 11 6 NAND |
||||
|
X6 3 11 12 6 NAND |
||||
|
X7 10 11 13 6 NAND |
||||
|
X8 12 13 4 6 NAND |
||||
|
X9 11 7 5 6 NAND |
||||
|
.ENDS ONEBIT |
||||
|
|
||||
|
.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 |
||||
|
* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, |
||||
|
* CARRY-IN, CARRY-OUT, VCC |
||||
|
X1 1 2 7 5 10 9 ONEBIT |
||||
|
X2 3 4 10 6 8 9 ONEBIT |
||||
|
.ENDS TWOBIT |
||||
|
|
||||
|
.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
||||
|
* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), |
||||
|
* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC |
||||
|
X1 1 2 3 4 9 10 13 16 15 TWOBIT |
||||
|
X2 5 6 7 8 11 12 16 14 15 TWOBIT |
||||
|
.ENDS FOURBIT |
||||
|
|
||||
|
*** DEFINE NOMINAL CIRCUIT |
||||
|
.MODEL DMOD D |
||||
|
.MODEL QMOD NPN(BF=75 RB=100 CJE=1PF CJC=3PF) |
||||
|
VCC 99 0 DC 5V |
||||
|
VIN1A 1 0 PULSE(0 3 0 10NS 10NS 10NS 50NS) |
||||
|
VIN1B 2 0 PULSE(0 3 0 10NS 10NS 20NS 100NS) |
||||
|
VIN2A 3 0 PULSE(0 3 0 10NS 10NS 40NS 200NS) |
||||
|
VIN2B 4 0 PULSE(0 3 0 10NS 10NS 80NS 400NS) |
||||
|
VIN3A 5 0 PULSE(0 3 0 10NS 10NS 160NS 800NS) |
||||
|
VIN3B 6 0 PULSE(0 3 0 10NS 10NS 320NS 1600NS) |
||||
|
VIN4A 7 0 PULSE(0 3 0 10NS 10NS 640NS 3200NS) |
||||
|
VIN4B 8 0 PULSE(0 3 0 10NS 10NS 1280NS 6400NS) |
||||
|
X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT |
||||
|
RBIT0 9 0 1K |
||||
|
RBIT1 10 0 1K |
||||
|
RBIT2 11 0 1K |
||||
|
RBIT3 12 0 1K |
||||
|
RCOUT 13 0 1K |
||||
|
|
||||
|
*** (FOR THOSE WITH MONEY (AND MEMORY) TO BURN) |
||||
|
.option noinit acct |
||||
|
.TRAN 1NS 6400NS |
||||
|
*.save VIN1A VIN1B VIN2A VIN2B VIN3A VIN3B VIN4A VIN4B |
||||
|
* save inputs |
||||
|
.save V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8) |
||||
|
* save outputs |
||||
|
.save V(9) V(10) V(11) V(12) V(13) |
||||
|
*.options savecurrents |
||||
|
*.save alli |
||||
|
|
||||
|
.control |
||||
|
run |
||||
|
rusage |
||||
|
* plot the inputs, use offset to plot on top of each other |
||||
|
plot v(1) v(2)+4 v(3)+8 v(4)+12 v(5)+16 v(6)+20 v(7)+24 v(8)+28 |
||||
|
* plot the outputs, use offset to plot on top of each other |
||||
|
plot v(9) v(10)+4 v(11)+8 v(12)+12 v(13)+16 |
||||
|
.endc |
||||
|
|
||||
|
.END |
||||
|
|
||||
|
|
||||
@ -0,0 +1,79 @@ |
|||||
|
ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER |
||||
|
|
||||
|
*** SUBCIRCUIT DEFINITIONS |
||||
|
.SUBCKT NAND in1 in2 out VDD |
||||
|
* NODES: INPUT(2), OUTPUT, VCC |
||||
|
M1 out in2 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p |
||||
|
M2 net.1 in2 0 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p |
||||
|
M3 out in1 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p |
||||
|
M4 out in1 net.1 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p |
||||
|
.ENDS NAND |
||||
|
|
||||
|
.SUBCKT ONEBIT 1 2 3 4 5 6 |
||||
|
* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC |
||||
|
X1 1 2 7 6 NAND |
||||
|
X2 1 7 8 6 NAND |
||||
|
X3 2 7 9 6 NAND |
||||
|
X4 8 9 10 6 NAND |
||||
|
X5 3 10 11 6 NAND |
||||
|
X6 3 11 12 6 NAND |
||||
|
X7 10 11 13 6 NAND |
||||
|
X8 12 13 4 6 NAND |
||||
|
X9 11 7 5 6 NAND |
||||
|
.ENDS ONEBIT |
||||
|
|
||||
|
.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 |
||||
|
* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, |
||||
|
* CARRY-IN, CARRY-OUT, VCC |
||||
|
X1 1 2 7 5 10 9 ONEBIT |
||||
|
X2 3 4 10 6 8 9 ONEBIT |
||||
|
.ENDS TWOBIT |
||||
|
|
||||
|
.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
||||
|
* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), |
||||
|
* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC |
||||
|
X1 1 2 3 4 9 10 13 16 15 TWOBIT |
||||
|
X2 5 6 7 8 11 12 16 14 15 TWOBIT |
||||
|
.ENDS FOURBIT |
||||
|
|
||||
|
*** POWER |
||||
|
VCC 99 0 DC 3.3V |
||||
|
|
||||
|
*** ALL INPUTS |
||||
|
VIN1A 1 0 DC 0 PULSE(0 3 0 5NS 5NS 20NS 50NS) |
||||
|
VIN1B 2 0 DC 0 PULSE(0 3 0 5NS 5NS 30NS 100NS) |
||||
|
VIN2A 3 0 DC 0 PULSE(0 3 0 5NS 5NS 50NS 200NS) |
||||
|
VIN2B 4 0 DC 0 PULSE(0 3 0 5NS 5NS 90NS 400NS) |
||||
|
VIN3A 5 0 DC 0 PULSE(0 3 0 5NS 5NS 170NS 800NS) |
||||
|
VIN3B 6 0 DC 0 PULSE(0 3 0 5NS 5NS 330NS 1600NS) |
||||
|
VIN4A 7 0 DC 0 PULSE(0 3 0 5NS 5NS 650NS 3200NS) |
||||
|
VIN4B 8 0 DC 0 PULSE(0 3 0 5NS 5NS 1290NS 6400NS) |
||||
|
|
||||
|
*** DEFINE NOMINAL CIRCUIT |
||||
|
X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT |
||||
|
|
||||
|
.option noinit acct |
||||
|
.TRAN 500p 6400NS |
||||
|
* save inputs |
||||
|
.save V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8) |
||||
|
|
||||
|
* use BSIM3 model with default parameters |
||||
|
.model n1 nmos level=49 version=3.3.0 |
||||
|
.model p1 pmos level=49 version=3.3.0 |
||||
|
*.include ./Modelcards/modelcard32.nmos |
||||
|
*.include ./Modelcards/modelcard32.pmos |
||||
|
|
||||
|
.control |
||||
|
pre_set strict_errorhandling |
||||
|
unset ngdebug |
||||
|
*save outputs and specials |
||||
|
save x1.x1.x1.7 V(9) V(10) V(11) V(12) V(13) |
||||
|
run |
||||
|
rusage |
||||
|
* plot the inputs, use offset to plot on top of each other |
||||
|
plot v(1) v(2)+4 v(3)+8 v(4)+12 v(5)+16 v(6)+20 v(7)+24 v(8)+28 |
||||
|
* plot the outputs, use offset to plot on top of each other |
||||
|
plot v(9) v(10)+4 v(11)+8 v(12)+12 v(13)+16 |
||||
|
.endc |
||||
|
|
||||
|
.END |
||||
@ -0,0 +1,10 @@ |
|||||
|
# tcl script for gtkwave: show vcd file data created by ngspice |
||||
|
set nfacs [ gtkwave::getNumFacs ] |
||||
|
|
||||
|
for {set i 0} {$i < $nfacs } {incr i} { |
||||
|
set facname [ gtkwave::getFacName $i ] |
||||
|
set num_added [ gtkwave::addSignalsFromList $facname ] |
||||
|
} |
||||
|
|
||||
|
gtkwave::/Edit/UnHighlight_All |
||||
|
gtkwave::/Time/Zoom/Zoom_Full |
||||
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