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@ -22,248 +22,248 @@ R201 -5V 9 22 |
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Rref1in VU100in- VU780out 9130 |
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Rref1fb VU1bias+ VU100in- 33 |
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XU101 +5V 7 0 6 VU780out 8 AD780A |
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* AD780A SPICE Macromodel 5/93, Rev. A |
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* AAG / PMI |
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* |
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* This version of the AD780 voltage reference model simulates the worst case |
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* parameters of the 'A' grade. The worst case parameters used |
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* correspond to those in the data sheet. |
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* |
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* Copyright 1993 by Analog Devices, Inc. |
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* |
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* Refer to "README.DOC" file for License Statement. Use of this model |
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* indicates your acceptance with the terms and provisions in the License Statement. |
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* |
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* NODE NUMBERS |
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* VIN |
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* | TEMP |
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* | | GND |
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* | | | TRIM |
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* | | | | VOUT |
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* | | | | | RANGE |
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* | | | | | | |
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.SUBCKT AD780A 2 3 4 5 6 8 |
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* |
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* BANDGAP REFERENCE |
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* |
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I1 4 40 DC 1.21174E-3 |
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R1 40 4 1E3 TC=7E-6 |
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EN 10 40 42 0 1 |
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G1 4 10 2 4 4.85668E-9 |
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F1 4 10 POLY(2) VS1 VS2 (0,2.42834E-5,3.8E-5) |
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Q1 2 10 11 QT |
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I2 11 4 DC 12.84E-6 |
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R2 11 3 1E3 |
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I3 3 4 DC 0 |
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* |
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* NOISE VOLTAGE GENERATOR |
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* |
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VN1 41 0 DC 2 |
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DN1 41 42 DEN |
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DN2 42 43 DEN |
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VN2 0 43 DC 2 |
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* |
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* INTERNAL OP AMP |
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* |
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G2 4 12 10 20 1.93522E-4 |
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R3 12 4 2.5837E9 |
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C1 12 4 6.8444E-11 |
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D1 12 13 DX |
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V1 2 13 DC 1.2 |
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* |
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* SECONDARY POLE @ 508 kHz |
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* |
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G3 4 14 12 4 1E-6 |
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R4 14 4 1E6 |
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C2 14 4 3.1831E-13 |
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* |
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* OUTPUT STAGE |
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* |
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ISY 2 4 6.8282E-4 |
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FSY 2 4 V1 -1 |
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RSY 2 4 500E3 |
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* |
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G4 4 15 14 4 25E-6 |
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R5 15 4 40E3 |
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Q2 4 15 16 QP |
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I4 2 16 DC 100E-6 |
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Q3 4 16 18 QP |
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R6 18 23 15 |
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R7 16 21 150E3 |
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R8 2 17 34.6 |
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Q4 17 16 19 QN |
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R9 21 20 6.46E3 |
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R10 20 4 6.1E3 |
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R11 20 5 53E3 |
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R12 20 8 15.6E3 |
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I5 5 4 DC 0 |
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I6 8 4 DC 0 |
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VS1 21 19 DC 0 |
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VS2 23 21 DC 0 |
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L1 21 6 1E-7 |
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* |
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* OUTPUT CURRENT LIMIT |
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* |
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FSC 15 4 VSC 1 |
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VSC 2 22 DC 0 |
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QSC 22 2 17 QN |
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* |
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.MODEL QT NPN(IS=1.68E-16 BF=1E4) |
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.MODEL QN NPN(IS=1E-15 BF=1E3) |
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.MODEL QP PNP(IS=1E-15 BF=1E3) |
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.MODEL DX D(IS=1E-15) |
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.MODEL DEN D(IS=1E-12 RS=2.425E+05 AF=1 KF=6.969E-16) |
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.ENDS AD780A |
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* AD780A SPICE Macromodel 5/93, Rev. A |
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* AAG / PMI |
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* |
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* This version of the AD780 voltage reference model simulates the worst case |
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* parameters of the 'A' grade. The worst case parameters used |
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* correspond to those in the data sheet. |
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* |
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* Copyright 1993 by Analog Devices, Inc. |
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* |
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* Refer to "README.DOC" file for License Statement. Use of this model |
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* indicates your acceptance with the terms and provisions in the License Statement. |
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* |
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* NODE NUMBERS |
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* VIN |
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* | TEMP |
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* | | GND |
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* | | | TRIM |
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* | | | | VOUT |
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* | | | | | RANGE |
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* | | | | | | |
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.SUBCKT AD780A 2 3 4 5 6 8 |
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* |
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* BANDGAP REFERENCE |
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* |
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I1 4 40 DC 1.21174E-3 |
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R1 40 4 1E3 TC=7E-6 |
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EN 10 40 42 0 1 |
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G1 4 10 2 4 4.85668E-9 |
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F1 4 10 POLY(2) VS1 VS2 (0,2.42834E-5,3.8E-5) |
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Q1 2 10 11 QT |
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I2 11 4 DC 12.84E-6 |
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R2 11 3 1E3 |
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I3 3 4 DC 0 |
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* |
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* NOISE VOLTAGE GENERATOR |
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* |
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VN1 41 0 DC 2 |
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DN1 41 42 DEN |
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DN2 42 43 DEN |
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VN2 0 43 DC 2 |
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* |
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* INTERNAL OP AMP |
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* |
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G2 4 12 10 20 1.93522E-4 |
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R3 12 4 2.5837E9 |
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C1 12 4 6.8444E-11 |
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D1 12 13 DX |
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V1 2 13 DC 1.2 |
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* |
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* SECONDARY POLE @ 508 kHz |
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* |
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G3 4 14 12 4 1E-6 |
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R4 14 4 1E6 |
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C2 14 4 3.1831E-13 |
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* |
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* OUTPUT STAGE |
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* |
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ISY 2 4 6.8282E-4 |
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FSY 2 4 V1 -1 |
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RSY 2 4 500E3 |
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* |
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G4 4 15 14 4 25E-6 |
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R5 15 4 40E3 |
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Q2 4 15 16 QP |
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I4 2 16 DC 100E-6 |
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Q3 4 16 18 QP |
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R6 18 23 15 |
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R7 16 21 150E3 |
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R8 2 17 34.6 |
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Q4 17 16 19 QN |
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R9 21 20 6.46E3 |
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R10 20 4 6.1E3 |
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R11 20 5 53E3 |
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R12 20 8 15.6E3 |
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I5 5 4 DC 0 |
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I6 8 4 DC 0 |
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VS1 21 19 DC 0 |
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VS2 23 21 DC 0 |
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L1 21 6 1E-7 |
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* |
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* OUTPUT CURRENT LIMIT |
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* |
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FSC 15 4 VSC 1 |
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VSC 2 22 DC 0 |
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QSC 22 2 17 QN |
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* |
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.MODEL QT NPN(level=1 IS=1.68E-16 BF=1E4) |
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.MODEL QN NPN(level=1 IS=1E-15 BF=1E3) |
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.MODEL QP PNP(level=1 IS=1E-15 BF=1E3) |
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.MODEL DX D(IS=1E-15) |
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.MODEL DEN D(IS=1E-12 RS=2.425E+05 AF=1 KF=6.969E-16) |
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.ENDS AD780A |
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C101 0 U100V- 1uF |
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C102 U100V+ 0 1uF |
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XU100 0 VU100in- U100V+ U100V- VU1bias+ OP177A |
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* OP177A SPICE Macro-model 12/90, Rev. B |
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* JCB / PMI |
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* |
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* Revision History: |
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* REV. B |
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* Re-ordered subcircuit call out nodes to put the |
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* output node last. |
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* Changed Ios from 1E-9 to 0.5E-9 |
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* Added F1 and F2 to fix short circuit current limit. |
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* |
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* |
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* This version of the OP-177 model simulates the worst case |
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* parameters of the 'A' grade. The worst case parameters |
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* used correspond to those in the data book. |
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* |
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* |
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* Copyright 1990 by Analog Devices, Inc. |
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* |
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* Refer to "README.DOC" file for License Statement. Use of this model |
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* indicates your acceptance with the terms and provisions in the License Statement. |
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* |
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* Node assignments |
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* non-inverting input |
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* | inverting input |
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* | | positive supply |
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* | | | negative supply |
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* | | | | output |
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* | | | | | |
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.SUBCKT OP177A 1 2 99 50 39 |
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* |
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* INPUT STAGE & POLE AT 6 MHZ |
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* |
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R1 2 3 5E11 |
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R2 1 3 5E11 |
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R3 5 97 0.0606 |
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R4 6 97 0.0606 |
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CIN 1 2 4E-12 |
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C2 5 6 218.9E-9 |
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I1 4 51 1 |
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IOS 1 2 0.5E-9 |
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EOS 9 10 POLY(1) 30 33 10E-6 1 |
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Q1 5 2 7 QX |
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Q2 6 9 8 QX |
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R5 7 4 0.009 |
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R6 8 4 0.009 |
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D1 2 1 DX |
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D2 1 2 DX |
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EN 10 1 12 0 1 |
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GN1 0 2 15 0 1 |
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GN2 0 1 18 0 1 |
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* |
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EREF 98 0 33 0 1 |
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EPLUS 97 0 99 0 1 |
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ENEG 51 0 50 0 1 |
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* |
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* VOLTAGE NOISE SOURCE WITH FLICKER NOISE |
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* |
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DN1 11 12 DEN |
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DN2 12 13 DEN |
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VN1 11 0 DC 2 |
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VN2 0 13 DC 2 |
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* |
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* CURRENT NOISE SOURCE WITH FLICKER NOISE |
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* |
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DN3 14 15 DIN |
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DN4 15 16 DIN |
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VN3 14 0 DC 2 |
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VN4 0 16 DC 2 |
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* |
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* SECOND CURRENT NOISE SOURCE |
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* |
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DN5 17 18 DIN |
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DN6 18 19 DIN |
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VN5 17 0 DC 2 |
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VN6 0 19 DC 2 |
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* |
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* FIRST GAIN STAGE |
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* |
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R7 20 98 1 |
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G1 98 20 5 6 119.8 |
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D3 20 21 DX |
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D4 22 20 DX |
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E1 97 21 POLY(1) 97 33 -2.4 1 |
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E2 22 51 POLY(1) 33 51 -2.4 1 |
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* |
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* GAIN STAGE & DOMINANT POLE AT 0.127 HZ |
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* |
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R8 23 98 1.253E9 |
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C3 23 98 1E-9 |
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G2 98 23 20 33 33.3E-6 |
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V1 97 24 1.8 |
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V2 25 51 1.8 |
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D5 23 24 DX |
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D6 25 23 DX |
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* |
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* NEGATIVE ZERO AT -4MHZ |
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* |
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R9 26 27 1 |
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C4 26 27 -39.75E-9 |
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R10 27 98 1E-6 |
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E3 26 98 23 33 1E6 |
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* |
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* COMMON-MODE GAIN NETWORK WITH ZERO AT 63 HZ |
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* |
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R13 30 31 1 |
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L2 31 98 2.52E-3 |
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G4 98 30 3 33 0.316E-6 |
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D7 30 97 DX |
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D8 51 30 DX |
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* |
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* POLE AT 2 MHZ |
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* |
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R14 32 98 1 |
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C5 32 98 79.5E-9 |
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G5 98 32 27 33 1 |
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* |
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* OUTPUT STAGE |
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* |
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R15 33 97 1 |
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R16 33 51 1 |
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GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3 |
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F1 34 0 V3 1 |
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F2 0 34 V4 1 |
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R17 34 99 400 |
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R18 34 50 400 |
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L3 34 39 2E-7 |
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G6 37 50 32 34 2.5E-3 |
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G7 38 50 34 32 2.5E-3 |
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G8 34 99 99 32 2.5E-3 |
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G9 50 34 32 50 2.5E-3 |
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V3 35 34 6.8 |
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V4 34 36 4.4 |
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D9 32 35 DX |
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D10 36 32 DX |
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D11 99 37 DX |
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D12 99 38 DX |
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D13 50 37 DY |
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D14 50 38 DY |
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* |
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* MODELS USED |
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* |
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.MODEL QX NPN(BF=333.3E6) |
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.MODEL DX D(IS=1E-15) |
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.MODEL DY D(IS=1E-15 BV=50) |
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.MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1) |
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.MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1) |
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.ENDS |
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* OP177A SPICE Macro-model 12/90, Rev. B |
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* JCB / PMI |
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* |
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* Revision History: |
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* REV. B |
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* Re-ordered subcircuit call out nodes to put the |
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* output node last. |
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* Changed Ios from 1E-9 to 0.5E-9 |
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* Added F1 and F2 to fix short circuit current limit. |
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* |
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* |
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* This version of the OP-177 model simulates the worst case |
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* parameters of the 'A' grade. The worst case parameters |
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* used correspond to those in the data book. |
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* |
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* |
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* Copyright 1990 by Analog Devices, Inc. |
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* |
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* Refer to "README.DOC" file for License Statement. Use of this model |
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* indicates your acceptance with the terms and provisions in the License Statement. |
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* |
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* Node assignments |
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* non-inverting input |
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* | inverting input |
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* | | positive supply |
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* | | | negative supply |
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* | | | | output |
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* | | | | | |
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.SUBCKT OP177A 1 2 99 50 39 |
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* |
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* INPUT STAGE & POLE AT 6 MHZ |
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* |
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R1 2 3 5E11 |
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R2 1 3 5E11 |
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R3 5 97 0.0606 |
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R4 6 97 0.0606 |
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CIN 1 2 4E-12 |
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C2 5 6 218.9E-9 |
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I1 4 51 1 |
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IOS 1 2 0.5E-9 |
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EOS 9 10 POLY(1) 30 33 10E-6 1 |
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Q1 5 2 7 QX |
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Q2 6 9 8 QX |
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R5 7 4 0.009 |
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R6 8 4 0.009 |
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D1 2 1 DX |
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D2 1 2 DX |
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EN 10 1 12 0 1 |
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GN1 0 2 15 0 1 |
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GN2 0 1 18 0 1 |
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* |
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EREF 98 0 33 0 1 |
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EPLUS 97 0 99 0 1 |
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ENEG 51 0 50 0 1 |
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* |
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* VOLTAGE NOISE SOURCE WITH FLICKER NOISE |
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* |
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DN1 11 12 DEN |
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DN2 12 13 DEN |
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VN1 11 0 DC 2 |
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VN2 0 13 DC 2 |
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* |
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* CURRENT NOISE SOURCE WITH FLICKER NOISE |
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* |
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DN3 14 15 DIN |
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DN4 15 16 DIN |
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VN3 14 0 DC 2 |
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VN4 0 16 DC 2 |
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* |
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* SECOND CURRENT NOISE SOURCE |
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* |
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DN5 17 18 DIN |
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DN6 18 19 DIN |
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VN5 17 0 DC 2 |
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VN6 0 19 DC 2 |
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* |
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* FIRST GAIN STAGE |
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* |
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R7 20 98 1 |
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G1 98 20 5 6 119.8 |
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D3 20 21 DX |
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|
|
D4 22 20 DX |
|
|
|
E1 97 21 POLY(1) 97 33 -2.4 1 |
|
|
|
E2 22 51 POLY(1) 33 51 -2.4 1 |
|
|
|
* |
|
|
|
* GAIN STAGE & DOMINANT POLE AT 0.127 HZ |
|
|
|
* |
|
|
|
R8 23 98 1.253E9 |
|
|
|
C3 23 98 1E-9 |
|
|
|
G2 98 23 20 33 33.3E-6 |
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|
|
V1 97 24 1.8 |
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|
|
V2 25 51 1.8 |
|
|
|
D5 23 24 DX |
|
|
|
D6 25 23 DX |
|
|
|
* |
|
|
|
* NEGATIVE ZERO AT -4MHZ |
|
|
|
* |
|
|
|
R9 26 27 1 |
|
|
|
C4 26 27 -39.75E-9 |
|
|
|
R10 27 98 1E-6 |
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|
|
E3 26 98 23 33 1E6 |
|
|
|
* |
|
|
|
* COMMON-MODE GAIN NETWORK WITH ZERO AT 63 HZ |
|
|
|
* |
|
|
|
R13 30 31 1 |
|
|
|
L2 31 98 2.52E-3 |
|
|
|
G4 98 30 3 33 0.316E-6 |
|
|
|
D7 30 97 DX |
|
|
|
D8 51 30 DX |
|
|
|
* |
|
|
|
* POLE AT 2 MHZ |
|
|
|
* |
|
|
|
R14 32 98 1 |
|
|
|
C5 32 98 79.5E-9 |
|
|
|
G5 98 32 27 33 1 |
|
|
|
* |
|
|
|
* OUTPUT STAGE |
|
|
|
* |
|
|
|
R15 33 97 1 |
|
|
|
R16 33 51 1 |
|
|
|
GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3 |
|
|
|
F1 34 0 V3 1 |
|
|
|
F2 0 34 V4 1 |
|
|
|
R17 34 99 400 |
|
|
|
R18 34 50 400 |
|
|
|
L3 34 39 2E-7 |
|
|
|
G6 37 50 32 34 2.5E-3 |
|
|
|
G7 38 50 34 32 2.5E-3 |
|
|
|
G8 34 99 99 32 2.5E-3 |
|
|
|
G9 50 34 32 50 2.5E-3 |
|
|
|
V3 35 34 6.8 |
|
|
|
V4 34 36 4.4 |
|
|
|
D9 32 35 DX |
|
|
|
D10 36 32 DX |
|
|
|
D11 99 37 DX |
|
|
|
D12 99 38 DX |
|
|
|
D13 50 37 DY |
|
|
|
D14 50 38 DY |
|
|
|
* |
|
|
|
* MODELS USED |
|
|
|
* |
|
|
|
.MODEL QX NPN(level=1 BF=333.3E6) |
|
|
|
.MODEL DX D(IS=1E-15) |
|
|
|
.MODEL DY D(IS=1E-15 BV=50) |
|
|
|
.MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1) |
|
|
|
.MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1) |
|
|
|
.ENDS |
|
|
|
R102 U100V+ +5V 22 |
|
|
|
R101 -5V U100V- 22 |
|
|
|
R98 0 VU2bias+ 1K |
|
|
|
@ -290,149 +290,149 @@ R26 2 VU2in- 150 |
|
|
|
R11 Vout2 VU2in- 180 |
|
|
|
XU2 VU2bias+ VU2in- V2+ V2- Vout2 AD8009an |
|
|
|
XU1 VU1bias+ VU1in- V1+ V1- Vout1 AD8009an |
|
|
|
***** AD8009 SPICE model Rev B SMR/ADI 8-21-97 |
|
|
|
|
|
|
|
* Copyright 1997 by Analog Devices, Inc. |
|
|
|
|
|
|
|
* Refer to "README.DOC" file for License Statement. Use of this model |
|
|
|
* indicates your acceptance with the terms and provisions in the License Statement. |
|
|
|
|
|
|
|
* rev B of this model corrects a problem in the output stage that would not |
|
|
|
* correctly reflect the output current to the voltage supplies |
|
|
|
|
|
|
|
* This model will give typical performance characteristics |
|
|
|
* for the following parameters; |
|
|
|
|
|
|
|
* closed loop gain and phase vs bandwidth |
|
|
|
* output current and voltage limiting |
|
|
|
* offset voltage (is static, will not vary with vcm) |
|
|
|
* ibias (again, is static, will not vary with vcm) |
|
|
|
* slew rate and step response performance |
|
|
|
* (slew rate is based on 10-90% of step response) |
|
|
|
* current on output will be reflected to the supplies |
|
|
|
* vnoise, referred to the input |
|
|
|
* inoise, referred to the input |
|
|
|
|
|
|
|
* distortion is not characterized |
|
|
|
|
|
|
|
* Node assignments |
|
|
|
* non-inverting input |
|
|
|
* | inverting input |
|
|
|
* | | positive supply |
|
|
|
* | | | negative supply |
|
|
|
* | | | | output |
|
|
|
* | | | | | |
|
|
|
.SUBCKT AD8009an 1 2 99 50 28 |
|
|
|
|
|
|
|
* input stage * |
|
|
|
|
|
|
|
q1 50 3 5 qp1 |
|
|
|
q2 99 5 4 qn1 |
|
|
|
q3 99 3 6 qn2 |
|
|
|
q4 50 6 4 qp2 |
|
|
|
i1 99 5 1.625e-3 |
|
|
|
i2 6 50 1.625e-3 |
|
|
|
cin1 1 98 2.6e-12 |
|
|
|
cin2 2 98 1e-12 |
|
|
|
v1 4 2 0 |
|
|
|
|
|
|
|
* input error sources * |
|
|
|
|
|
|
|
eos 3 1 poly(1) 20 98 2e-3 1 |
|
|
|
fbn 2 98 poly(1) vnoise3 50e-6 1e-3 |
|
|
|
fbp 1 98 poly(1) vnoise3 50e-6 1e-3 |
|
|
|
|
|
|
|
* slew limiting stage * |
|
|
|
|
|
|
|
fsl 98 16 v1 1 |
|
|
|
dsl1 98 16 d1 |
|
|
|
dsl2 16 98 d1 |
|
|
|
dsl3 16 17 d1 |
|
|
|
dsl4 17 16 d1 |
|
|
|
rsl 17 18 0.22 |
|
|
|
vsl 18 98 0 |
|
|
|
|
|
|
|
* gain stage * |
|
|
|
|
|
|
|
f1 98 7 vsl 2 |
|
|
|
rgain 7 98 2.5e5 |
|
|
|
cgain 7 98 1.25e-12 |
|
|
|
dcl1 7 8 d1 |
|
|
|
dcl2 9 7 d1 |
|
|
|
vcl1 99 8 1.83 |
|
|
|
vcl2 9 50 1.83 |
|
|
|
|
|
|
|
gcm 98 7 poly(2) 98 0 30 0 0 1e-5 1e-5 |
|
|
|
|
|
|
|
* second pole * |
|
|
|
|
|
|
|
epole 14 98 7 98 1 |
|
|
|
rpole 14 15 1 |
|
|
|
cpole 15 98 2e-10 |
|
|
|
|
|
|
|
* reference stage * |
|
|
|
|
|
|
|
eref 98 0 poly(2) 99 0 50 0 0 0.5 0.5 |
|
|
|
|
|
|
|
ecmref 30 0 poly(2) 1 0 2 0 0 0.5 0.5 |
|
|
|
|
|
|
|
* vnoise stage * |
|
|
|
|
|
|
|
rnoise1 19 98 4.6e-3 |
|
|
|
vnoise1 19 98 0 |
|
|
|
vnoise2 21 98 0.53 |
|
|
|
dnoise1 21 19 dn |
|
|
|
|
|
|
|
fnoise1 20 98 vnoise1 1 |
|
|
|
rnoise2 20 98 1 |
|
|
|
|
|
|
|
* inoise stage * |
|
|
|
|
|
|
|
rnoise3 22 98 8.18e-6 |
|
|
|
vnoise3 22 98 0 |
|
|
|
vnoise4 24 98 0.575 |
|
|
|
dnoise2 24 22 dn |
|
|
|
|
|
|
|
fnoise2 23 98 vnoise3 1 |
|
|
|
rnoise4 23 98 1 |
|
|
|
|
|
|
|
* buffer stage * |
|
|
|
|
|
|
|
gbuf 98 13 15 98 1e-2 |
|
|
|
rbuf 98 13 1e2 |
|
|
|
|
|
|
|
* output current reflected to supplies * |
|
|
|
|
|
|
|
fcurr 98 40 voc 1 |
|
|
|
vcur1 26 98 0 |
|
|
|
vcur2 98 27 0 |
|
|
|
dcur1 40 26 d1 |
|
|
|
dcur2 27 40 d1 |
|
|
|
|
|
|
|
* output stage * |
|
|
|
|
|
|
|
vo1 99 90 0 |
|
|
|
vo2 91 50 0 |
|
|
|
fout1 0 99 poly(2) vo1 vcur1 -9.27e-3 1 -1 |
|
|
|
fout2 50 0 poly(2) vo2 vcur2 -9.27e-3 1 -1 |
|
|
|
gout1 90 10 13 99 0.5 |
|
|
|
gout2 91 10 13 50 0.5 |
|
|
|
rout1 10 90 2 |
|
|
|
rout2 10 91 2 |
|
|
|
voc 10 28 0 |
|
|
|
rout3 28 98 1e6 |
|
|
|
dcl3 13 11 d1 |
|
|
|
dcl4 12 13 d1 |
|
|
|
vcl3 11 10 -0.445 |
|
|
|
vcl4 10 12 -0.445 |
|
|
|
|
|
|
|
.model qp1 pnp() |
|
|
|
.model qp2 pnp() |
|
|
|
.model qn1 npn() |
|
|
|
.model qn2 npn() |
|
|
|
.model d1 d() |
|
|
|
.model dn d(af=1 kf=1e-8) |
|
|
|
.ends |
|
|
|
***** AD8009 SPICE model Rev B SMR/ADI 8-21-97 |
|
|
|
|
|
|
|
* Copyright 1997 by Analog Devices, Inc. |
|
|
|
|
|
|
|
* Refer to "README.DOC" file for License Statement. Use of this model |
|
|
|
* indicates your acceptance with the terms and provisions in the License Statement. |
|
|
|
|
|
|
|
* rev B of this model corrects a problem in the output stage that would not |
|
|
|
* correctly reflect the output current to the voltage supplies |
|
|
|
|
|
|
|
* This model will give typical performance characteristics |
|
|
|
* for the following parameters; |
|
|
|
|
|
|
|
* closed loop gain and phase vs bandwidth |
|
|
|
* output current and voltage limiting |
|
|
|
* offset voltage (is static, will not vary with vcm) |
|
|
|
* ibias (again, is static, will not vary with vcm) |
|
|
|
* slew rate and step response performance |
|
|
|
* (slew rate is based on 10-90% of step response) |
|
|
|
* current on output will be reflected to the supplies |
|
|
|
* vnoise, referred to the input |
|
|
|
* inoise, referred to the input |
|
|
|
|
|
|
|
* distortion is not characterized |
|
|
|
|
|
|
|
* Node assignments |
|
|
|
* non-inverting input |
|
|
|
* | inverting input |
|
|
|
* | | positive supply |
|
|
|
* | | | negative supply |
|
|
|
* | | | | output |
|
|
|
* | | | | | |
|
|
|
.SUBCKT AD8009an 1 2 99 50 28 |
|
|
|
|
|
|
|
* input stage * |
|
|
|
|
|
|
|
q1 50 3 5 qp1 |
|
|
|
q2 99 5 4 qn1 |
|
|
|
q3 99 3 6 qn2 |
|
|
|
q4 50 6 4 qp2 |
|
|
|
i1 99 5 1.625e-3 |
|
|
|
i2 6 50 1.625e-3 |
|
|
|
cin1 1 98 2.6e-12 |
|
|
|
cin2 2 98 1e-12 |
|
|
|
v1 4 2 0 |
|
|
|
|
|
|
|
* input error sources * |
|
|
|
|
|
|
|
eos 3 1 poly(1) 20 98 2e-3 1 |
|
|
|
fbn 2 98 poly(1) vnoise3 50e-6 1e-3 |
|
|
|
fbp 1 98 poly(1) vnoise3 50e-6 1e-3 |
|
|
|
|
|
|
|
* slew limiting stage * |
|
|
|
|
|
|
|
fsl 98 16 v1 1 |
|
|
|
dsl1 98 16 d1 |
|
|
|
dsl2 16 98 d1 |
|
|
|
dsl3 16 17 d1 |
|
|
|
dsl4 17 16 d1 |
|
|
|
rsl 17 18 0.22 |
|
|
|
vsl 18 98 0 |
|
|
|
|
|
|
|
* gain stage * |
|
|
|
|
|
|
|
f1 98 7 vsl 2 |
|
|
|
rgain 7 98 2.5e5 |
|
|
|
cgain 7 98 1.25e-12 |
|
|
|
dcl1 7 8 d1 |
|
|
|
dcl2 9 7 d1 |
|
|
|
vcl1 99 8 1.83 |
|
|
|
vcl2 9 50 1.83 |
|
|
|
|
|
|
|
gcm 98 7 poly(2) 98 0 30 0 0 1e-5 1e-5 |
|
|
|
|
|
|
|
* second pole * |
|
|
|
|
|
|
|
epole 14 98 7 98 1 |
|
|
|
rpole 14 15 1 |
|
|
|
cpole 15 98 2e-10 |
|
|
|
|
|
|
|
* reference stage * |
|
|
|
|
|
|
|
eref 98 0 poly(2) 99 0 50 0 0 0.5 0.5 |
|
|
|
|
|
|
|
ecmref 30 0 poly(2) 1 0 2 0 0 0.5 0.5 |
|
|
|
|
|
|
|
* vnoise stage * |
|
|
|
|
|
|
|
rnoise1 19 98 4.6e-3 |
|
|
|
vnoise1 19 98 0 |
|
|
|
vnoise2 21 98 0.53 |
|
|
|
dnoise1 21 19 dn |
|
|
|
|
|
|
|
fnoise1 20 98 vnoise1 1 |
|
|
|
rnoise2 20 98 1 |
|
|
|
|
|
|
|
* inoise stage * |
|
|
|
|
|
|
|
rnoise3 22 98 8.18e-6 |
|
|
|
vnoise3 22 98 0 |
|
|
|
vnoise4 24 98 0.575 |
|
|
|
dnoise2 24 22 dn |
|
|
|
|
|
|
|
fnoise2 23 98 vnoise3 1 |
|
|
|
rnoise4 23 98 1 |
|
|
|
|
|
|
|
* buffer stage * |
|
|
|
|
|
|
|
gbuf 98 13 15 98 1e-2 |
|
|
|
rbuf 98 13 1e2 |
|
|
|
|
|
|
|
* output current reflected to supplies * |
|
|
|
|
|
|
|
fcurr 98 40 voc 1 |
|
|
|
vcur1 26 98 0 |
|
|
|
vcur2 98 27 0 |
|
|
|
dcur1 40 26 d1 |
|
|
|
dcur2 27 40 d1 |
|
|
|
|
|
|
|
* output stage * |
|
|
|
|
|
|
|
vo1 99 90 0 |
|
|
|
vo2 91 50 0 |
|
|
|
fout1 0 99 poly(2) vo1 vcur1 -9.27e-3 1 -1 |
|
|
|
fout2 50 0 poly(2) vo2 vcur2 -9.27e-3 1 -1 |
|
|
|
gout1 90 10 13 99 0.5 |
|
|
|
gout2 91 10 13 50 0.5 |
|
|
|
rout1 10 90 2 |
|
|
|
rout2 10 91 2 |
|
|
|
voc 10 28 0 |
|
|
|
rout3 28 98 1e6 |
|
|
|
dcl3 13 11 d1 |
|
|
|
dcl4 12 13 d1 |
|
|
|
vcl3 11 10 -0.445 |
|
|
|
vcl4 10 12 -0.445 |
|
|
|
|
|
|
|
.model qp1 pnp(level=1) |
|
|
|
.model qp2 pnp(level=1) |
|
|
|
.model qn1 npn(level=1) |
|
|
|
.model qn2 npn(level=1) |
|
|
|
.model d1 d() |
|
|
|
.model dn d(af=1 kf=1e-8) |
|
|
|
.ends |
|
|
|
R6 1 Vout1 250 |
|
|
|
C3 1 0 1.5pF |
|
|
|
V3 VU1in- Vinput DC 0V |
|
|
|
|