Replace $ in instance and.model lines by ;

$ is not a valid end-of-line comment delimiter when PS
compatibility mode is chosen.

examples/Monte_Carlo/OpWien.sp

@@ -24,10 +24,10 @@ VR2 r2  0 dc 0 trrandom (2 'ttime10' 0 1)  ; Gauss controlling voltage
 * If Gauss, factor 0.033 is 10% equivalent to 3 sigma
 * if uniform, uniform between +/- 10%
 R2 4 6  R = 'res + 0.033 * res*V(r2)'  ; behavioral resistor
-*R2 4 6 'res' $ constant R
+*R2 4 6 'res' ; constant R
 
 VC2 c2 0 dc 0  trrandom (2 'ttime10' 0 1)
-*C2	6 	3'cn'  $ constant C
+*C2	6 	3'cn'  ; constant C
 C2 6 3 C = 'cn + 0.033 * cn*V(c2)'  ; behavioral capacitor
 
 VR1 r1  0 dc 0 trrandom (2 'ttime10' 0 1)
@@ -74,7 +74,7 @@ ROUT	5	6	10
 .control
 option noinit
 run
-plot V(4) 5*V(r1) 5*V(r2) 5*V(c1) 5*V(c2)
+plot 5*V(r1) 5*V(r2) 5*V(c1) 5*V(c2) V(4)
 linearize v(4)
 fft v(4)
 let v4mag =  mag(v(4))

examples/cider/serial/pullup.cir

@@ -22,8 +22,8 @@ CL  4 0 5.0PF
 
 .MODEL M_NPN NBJT LEVEL=2
 + TITLE TWO-DIMENSIONAL NUMERICAL POLYSILICON EMITTER BIPOLAR TRANSISTOR
-+ $ SINCE ONLY HALF THE DEVICE IS SIMULATED, DOUBLE THE UNIT WIDTH TO GET
-+ $ 1.0 UM EMITTER.
++ ; SINCE ONLY HALF THE DEVICE IS SIMULATED, DOUBLE THE UNIT WIDTH TO GET
++ ; 1.0 UM EMITTER.
 + OPTIONS DEFW=2.0U
 + OUTPUT STATISTICS
 + 

examples/control_structs/s-param.cir

@@ -49,15 +49,15 @@ RS2 66 6 0.001
 RS3 22 6 1e12
 RS4 66 2 1e12
 *Driver
-Vacdc 1 0 DC 'Vbias_in' AC 1 $ ac voltage and dc bias at input (applied through load resistor)
+Vacdc 1 0 DC 'Vbias_in' AC 1 ; ac voltage and dc bias at input (applied through load resistor)
 R1 1 2 'Rbase'
-E1 3 0 2 0 2       $ amplify in port ac voltage by 2
-Vac 3 4 DC 0 AC 1  $ subtract driving ac voltage
+E1 3 0 2 0 2       ; amplify in port ac voltage by 2
+Vac 3 4 DC 0 AC 1  ; subtract driving ac voltage
 R_loop 4 5 0.001
-R3 5 0 1           $ ground return for measure node 5
+R3 5 0 1           ; ground return for measure node 5
 *Readout
-E2 7 0 6 0 2       $ amplify out port ac voltage by 2
-R4 6 8 'Rbase'     $ load resistor at output (ac)
+E2 7 0 6 0 2       ; amplify out port ac voltage by 2
+R4 6 8 'Rbase'     ; load resistor at output (ac)
 Vdc 8 0 DC 'Vbias_out' AC 0 $ dc bias at output (applied through load resistor)
 .ends
 

examples/various/nmos_pmos_BSIM330.sp

@@ -18,11 +18,11 @@ vbsp 44 0 0
 .model n1 nmos level=49 version=3.3.0 tox=3.5n nch=2.4e17 nsub=5e16 vth0=0.15
 .model p1 pmos level=49 version=3.3.0 tox=3.5n nch=2.5e17 nsub=5e16 vth0=-0.15
 
-*.include ./Modelcards/modelcard.nmos $ Berkeley model cards limited to L >= 0.35µm
-*.include ./Modelcards/modelcard.pmos $ Berkeley model cards limited to L >= 0.35µm
+*.include ./Modelcards/modelcard.nmos ; Berkeley model cards limited to L >= 0.35µm
+*.include ./Modelcards/modelcard.pmos ; Berkeley model cards limited to L >= 0.35µm
 
 * update of the default parameters required
-*.model n1 NMOS level=49 version=3.3.0 $ nearly no current due to VT > 2 V ?
+*.model n1 NMOS level=49 version=3.3.0 ; nearly no current due to VT > 2 V ?
 *.model p1 PMOS level=49 version=3.3.0
 
 .control

examples/various/tmp-noise.cir

@@ -4,10 +4,10 @@ v1  1 0  dc 2 ac 1
 v2  200 0 dc=1
 
 R1  1 2  1k
-R2  2 0  1k tc1=0.001 $ tc2=1e-5
+R2  2 0  1k tc1=0.001 ; tc2=1e-5
 
 R10 1 20 1k
-R20 20 0 '1k*v(200)' tc1=0.001 $ tc2=1e-5
+R20 20 0 '1k*v(200)' tc1=0.001 ; tc2=1e-5
 
 .temp 127.0
 

examples/vdmos/IXTH80N20L-IXTH48P20P-quasisat.sp

@@ -34,7 +34,7 @@ plot dc3.vs2#branch vs2#branch
 * David Zan, (c) 2017/03/02 Preliminary
 .MODEL IXTH80N20L VDMOS Nchan Vds=200
 + VTO=4 KP=15
-+ Lambda=3m  $ will be reset by altermod to original 2m
++ Lambda=3m  ; will be reset by altermod to original 2m
 + Mtriode=0.4
 + Ksubthres=120m
 + subshift=160m
@@ -46,12 +46,12 @@ plot dc3.vs2#branch vs2#branch
 + NBV=4
 + TT=250e-9
 + vq=100
-+ rq=0.5  $ will be reset by altermod to original 0
++ rq=0.5  ; will be reset by altermod to original 0
 
 * David Zan, (c) 2017/03/02 Preliminary
 .MODEL IXTH48P20P VDMOS Pchan Vds=200
 + VTO=-4 KP=10
-+ Lambda=7m  $ will be reset by altermod to original 5m  
++ Lambda=7m  ; will be reset by altermod to original 5m  
 + Mtriode=0.3   
 + Ksubthres=120m
 + Rs=10m Rd=20m Rds=200e6
@@ -62,6 +62,6 @@ plot dc3.vs2#branch vs2#branch
 + NBV=4
 + TT=260e-9
 + vq=100
-+ rq=0.5  $ will be reset by altermod to original 0
++ rq=0.5  ; will be reset by altermod to original 0
 
 .end

examples/vdmos/VDMOS-DIO.sp

@@ -10,7 +10,7 @@ m1 d g s IXTP6N100D2
 .MODEL IXTP6N100D2 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p a=1 TT=1371n IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 Vj=0.1 Cjo=3200pF ksubthres=0.1)
 
 Vd d 0 ac 1 dc -0.5 pwl(0 2 2.5 -0.5)
-Vg g 0 -5  $ transistor is off
+Vg g 0 -5  ; transistor is off
 Vs s 0 0
 
 .control