If a node name to be plotted ends by ':power', its type is set to POWER.

Thus 'settype power nodename(s)' in the examples is no longer necessary.

examples/probe/Dual-NMOS-amp.cir

@@ -55,7 +55,6 @@ plot tj1 tj2 tcase1 tcase2
 plot in out xlimit 6 6.04
 plot i(xu1:vcc-) i(xu1:vcc+)*(-1) xlimit 6 6.04
 plot @m1[id] + i(m1:d) xlimit 9 9.04
-settype power m1:power m2:power xu1:power
 plot  m1:power m2:power ylimit 11 21
 plot xu1:power
 meas tran m1power avg  m1:power

examples/probe/F5TurboV2-Probe.cir

@@ -34,7 +34,8 @@ RTH1 Net-_D3a1-Pad1_ Net-_R11-Pad1_ 4.7k
 XP1 Net-_P1-Pad1_ +32 +32 RPOT value=5k ratio=0.15
 R13 Net-_Q3-Pad2_ Net-_P1-Pad1_ 47.5
 MQ3 out Net-_Q3-Pad2_ Net-_D3a1-Pad1_ IRFP9240
-.probe p(MQ3, 3) p(MQ5, s)  ; <------------------------------------------
+.probe i(MQ3, 3) i(MQ5, s)  ; <------------------------------------------
+.probe p(MQ3) p(MQ5)  ; <------------------------------------------
 R18 +32 Net-_D3a1-Pad1_ 1
 R17 +32 Net-_D3a1-Pad1_ 1
 R7 out Net-_P3-Pad1_ 220
@@ -69,7 +70,6 @@ display
 rusage
 plot out in
 plot i(mq3:s) i(mq5:s)
-settype power mq3:power mq5:power
 plot mq3:power mq5:power
 meas tran mq3power avg mq3:power
 meas tran mq5power avg mq5:power

examples/probe/mos-test.cir

@@ -1,4 +1,4 @@
-.probe test with simple CMOS inverter
+.probe test with simple CMOS inverter, many buggy .probe commands
 
 Vd dd 0 dc 5
 Vin in 0 dc 0 PULSE (0 5 0 10n 10n 100n 200n)

examples/probe/probe-i-dev.cir

@@ -31,7 +31,6 @@ X1 c1 b1 e1 s1  pbip
 .control
 *op
 dc vbb 0 2 0.01
-settype power q1:power
 plot q1:power
 display
 *print all

src/frontend/outitf.c

@@ -953,6 +953,8 @@ guess_type(const char *name)
         type = SV_RES;
     else if (cieq(name, "i-sweep"))
         type = SV_CURRENT;
+    else if (strstr(name, ":power\0"))
+        type = SV_POWER;
     /* current source ISRC parameters for current */
     else if (substring("@i", name) && (substring("[c]", name) || substring("[dc]", name) || substring("[current]", name)))
             type = SV_CURRENT;