Further fix for PWL bugs introduced by 9c71db3 (Fix for Bug #607) and

partially fixed by 79c69e0 and 9c75367.  This also fixes Bug #468 -
"Bugs in src/spicelib/devices/vsrc/vsrcacct.c for PWL source."

src/spicelib/devices/vsrc/vsrcacct.c

@@ -172,7 +172,11 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel)
 
                                     period = end -
                                         here->VSRCcoeffs[here->VSRCrBreakpt];
+                                    time -=
+                                        here->VSRCcoeffs[here->VSRCrBreakpt];
                                     time -= period * floor(time / period);
+                                    time +=
+                                        here->VSRCcoeffs[here->VSRCrBreakpt];
                                 } else {
                                      here->VSRCbreak_time = ckt->CKTfinalTime;
                                      break;

src/spicelib/devices/vsrc/vsrcload.c

@@ -318,6 +318,7 @@ VSRCload(GENmodel *inModel, CKTcircuit *ckt)
 
                                 period = end_time -
                                     here->VSRCcoeffs[here->VSRCrBreakpt];
+                                time -= here->VSRCcoeffs[here->VSRCrBreakpt];
                                 time -= period * floor(time / period);
                                 time += here->VSRCcoeffs[here->VSRCrBreakpt];
                             } else {