include ./thing ---> include thing

ChangeLog

@@ -1,3 +1,19 @@
+2010-12-27  Robert Larice
+ * tests/bsim3soi/inv_dc.cir ,
+ * tests/bsim3soi/inv_tr.cir ,
+ * tests/bsim3soi/test1.cir ,
+ * tests/bsim3soi/test2.cir ,
+ * tests/bsim3soi/test3.cir ,
+ * tests/bsim3soi/test4.cir ,
+ * tests/bsim3soi/test5.cir ,
+ * tests/bsim3soi/test6.cir ,
+ * tests/bsim3soi/test7.cir ,
+ * tests/bsim3soi/test8.cir :
+    include ./thing   --->    include thing
+      ngspice currently has a broken include path semantic.
+      every pathname with a '/' in it is considered to be `absolute'
+	and the include path will not be applied
+
 2010-12-27  Robert Larice
  * src/spicelib/devices/isrc/isrcask.c :
     bug fix, missing isrc trnoise ask function

tests/bsim3soi/inv_dc.cir

@@ -1,8 +1,8 @@
 B4SOI  Drain Gate Source Back-gate(substrate) Body  Tx  W  L (body ommitted for FB)
 * Modified by Darsen Lu 03/11/2009
 
-.include ./nmos4p3.mod
-.include ./pmos4p3.mod
+.include nmos4p3.mod
+.include pmos4p3.mod
 .option TEMP=27C noacct
 
 Vpower VD 0 1.5

tests/bsim3soi/inv_tr.cir

@@ -1,8 +1,8 @@
 B4SOI  Drain Gate Source Back-gate(substrate) Body  Tx  W  L (body ommitted for FB)
 * Modified by Darsen Lu 03/11/2009
 
-.include ./nmos4p3.mod
-.include ./pmos4p3.mod
+.include nmos4p3.mod
+.include pmos4p3.mod
 .option TEMP=27C noacct
 
 Vpower VD 0 1.5

tests/bsim3soi/test1.cir

@@ -16,7 +16,7 @@ vp p 0 		0.0
 vb b 0 		0.0
 
 .dc vd 0 1.2 0.01 vg 0.2 1.2 0.1 
-.include ./nmos4p3.mod
+.include nmos4p3.mod
 .print dc i(vd) i(vs)
 .end
 

tests/bsim3soi/test2.cir

@@ -14,7 +14,7 @@ vs s 0 		0.0
 vp p 0 		0.0
 
 .dc vd 0 1.2 0.02 vg 0.4 1.2 0.1 
-.include ./nmos4p3.mod
+.include nmos4p3.mod
 .print dc i(vd)
 .end
 

tests/bsim3soi/test3.cir

@@ -14,7 +14,7 @@ vs s 0 		0.0
 vp p 0 		0.0
 
 .dc vg 0 1.2 0.02 vd 0.05 1.2 0.5 
-.include ./nmos4p3.mod
+.include nmos4p3.mod
 .print dc i(vd)
 .end
 

tests/bsim3soi/test4.cir

@@ -14,7 +14,7 @@ vs s 0 		0.0
 vp p 0 		0.0
 
 .dc vg 0 1.2 0.02 vd 0.05 1.2 0.5 
-.include ./nmos4p3.mod
+.include nmos4p3.mod
 .print dc i(vd)
 .end
 

tests/bsim3soi/test5.cir

@@ -14,7 +14,7 @@ vs s 0 		0.0
 vp p 0 		0.0
 
 .dc vd 0 -1.2 -0.02 vg -0.4 -1.2 -0.1 
-.include ./pmos4p3.mod
+.include pmos4p3.mod
 .print dc i(vd)
 .end
 

tests/bsim3soi/test6.cir

@@ -14,7 +14,7 @@ vs s 0 		0.0
 vp p 0 		0.0
 
 .dc vd 0 -1.2 -0.02 vg -0.4 -1.2 -0.1 
-.include ./pmos4p3.mod
+.include pmos4p3.mod
 .print dc i(vd)
 .end
 

tests/bsim3soi/test7.cir

@@ -14,7 +14,7 @@ vs s 0 		0.0
 vp p 0 		0.0
 
 .dc vg 0 -1.2 -0.02 vd -0.05 -1.2 -0.5 
-.include ./pmos4p3.mod
+.include pmos4p3.mod
 .print dc i(vd)
 .end
 

tests/bsim3soi/test8.cir

@@ -14,7 +14,7 @@ vs s 0 		0.0
 vp p 0 		0.0
 
 .dc vg 0 -1.2 -0.02 vd -0.05 -1.2 -0.5 
-.include ./pmos4p3.mod
+.include pmos4p3.mod
 .print dc i(vd)
 .end