From 8539029e6dd1aac88bce17ee433d874aae196a0f Mon Sep 17 00:00:00 2001
From: dwarning <dwarning>
Date: Thu, 12 Oct 2017 11:22:17 +0200
Subject: [PATCH] reduce simulation time for tcl examples

---
 examples/tclspice/tcl-testbench2/example.cir | 2 +-
 examples/tclspice/tcl-testbench4/example.cir | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/examples/tclspice/tcl-testbench2/example.cir b/examples/tclspice/tcl-testbench2/example.cir
index b31bb0993..34008f547 100644
--- a/examples/tclspice/tcl-testbench2/example.cir
+++ b/examples/tclspice/tcl-testbench2/example.cir
@@ -583,5 +583,5 @@ VARACTOR_V VARACTOR_V 0 DC 2.5
 .SAVE vddpower#branch 
 .SAVE vdd 
 .SAVE varactor_v 
-.TRAN 0.02n 3000n 0n 0.5n 
+.TRAN 0.02n 100n 0n 0.5n 
 .END
diff --git a/examples/tclspice/tcl-testbench4/example.cir b/examples/tclspice/tcl-testbench4/example.cir
index 4f8c41c20..b5aeaf426 100644
--- a/examples/tclspice/tcl-testbench4/example.cir
+++ b/examples/tclspice/tcl-testbench4/example.cir
@@ -579,5 +579,5 @@ EVLOGIC VRAMP 0 VSLEW 0 2.5
 VDDPOWER VDD VRAMP DC 0
 VARACTOR_V VARACTOR_V 0 DC 2.5
 
-.TRAN 0.02n 3000n 0n 0.5n 
+.TRAN 0.02n 100n 0n 0.5n 
 .END