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* src/spicelib/analysis/cktpzstr.c: Reversed a patch that went 

in between ng-spice-0.2 and ng-spice-0.3 that eliminated the
        following warnings: 'suggest parentheses around && within
        ||'.  The parenthesis were not placed correctly, leading to
        incorrect behaviour of the pole-zero analysis.

        * tests/polezero/*.out: Changed the content of these files because
        the bug that caused the incorrect pole-zero results have been
        traced to src/spicelib/analysis/cktpzstr.c.
pre-master-46
arno 26 years ago
parent
d902e99d6d
commit
9b7d4b3187
6 changed files with 121 additions and 12 deletions
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  1. 6
      ChangeLog
  2. 8
      src/spicelib/analysis/ChangeLog
  3. 24
      src/spicelib/analysis/cktpzstr.c
  4. 69
      tests/polezero/filt_bridge_t.out
  5. 16
      tests/polezero/filt_multistage.out
  6. 10
      tests/polezero/filt_rc.out

6
ChangeLog
View File

@ -1,3 +1,9 @@
2000-07-28 Arno W. Peters <A.W.Peters@ieee.org>
* tests/polezero/*.out: Changed the content of these files because
the bug that caused the incorrect pole-zero results have been
traced to src/spicelib/analysis/cktpzstr.c.
2000-07-05 Arno W. Peters <A.W.Peters@ieee.org> 2000-07-05 Arno W. Peters <A.W.Peters@ieee.org>
* src/devices/dev.c: Added first_device() and next_device() to * src/devices/dev.c: Added first_device() and next_device() to

8
src/spicelib/analysis/ChangeLog
View File

@ -1,3 +1,11 @@
2000-07-28 Arno W. Peters <A.W.Peters@ieee.org>
* cktpzstr.c: Reversed a patch that went in between ng-spice-0.2
and ng-spice-0.3 that eliminated the following warnings: 'suggest
parentheses around && within ||'. The parenthesis were not placed
correctly, leading to incorrect behaviour of the pole-zero
analysis.
2000-05-22 Paolo Nenzi <p.nenzi@ieee.org> 2000-05-22 Paolo Nenzi <p.nenzi@ieee.org>
* cktpzstr.c, cktsens.c: Applied Widlok patches. * cktpzstr.c, cktsens.c: Applied Widlok patches.

24
src/spicelib/analysis/cktpzstr.c
View File

@ -304,10 +304,10 @@ PZeval(int strat, PZtrial **set, PZtrial **new_trial_p)
new_trial->s.real = (set[1]->s.real + set[2]->s.real) / 2.0; new_trial->s.real = (set[1]->s.real + set[2]->s.real) / 2.0;
} }
} else if (CKTpzTrapped == 3) { } else if (CKTpzTrapped == 3) {
if ((new_trial->s.real <= set[0]->s.real
|| new_trial->s.real == set[1]->s.real)
&& (new_trial->s.imag == set[1]->s.imag
|| new_trial->s.real >= set[2]->s.real)) {
if (new_trial->s.real <= set[0]->s.real
|| new_trial->s.real == set[1]->s.real
&& new_trial->s.imag == set[1]->s.imag
|| new_trial->s.real >= set[2]->s.real) {
#ifdef PZDEBUG #ifdef PZDEBUG
DEBUG(1) DEBUG(1)
fprintf(stderr, fprintf(stderr,
@ -481,7 +481,7 @@ int CKTpzStrat(PZtrial **set)
/* minima in magnitude */ /* minima in magnitude */
/* Search for exact mag. minima, look for complex pair */ /* Search for exact mag. minima, look for complex pair */
suggestion = SYM; suggestion = SYM;
} else if ((a_mag > b_mag || a_mag == b_mag)
} else if (a_mag > b_mag || a_mag == b_mag
&& fabs(a) > fabs(b)) && fabs(a) > fabs(b))
suggestion = SPLIT_LEFT; suggestion = SPLIT_LEFT;
else else
@ -556,8 +556,8 @@ CKTpzRunTrial(CKTcircuit *ckt, PZtrial **new_trialp, PZtrial **set)
C_SUBEQ(diff_frac,p->s,new_trial->s); C_SUBEQ(diff_frac,p->s,new_trial->s);
if ((diff_frac.real < 0.0
|| diff_frac.real == 0.0) && diff_frac.imag < 0.0) {
if (diff_frac.real < 0.0
|| diff_frac.real == 0.0 && diff_frac.imag < 0.0) {
prev = p; prev = p;
if (p->flags & ISAMINIMA) if (p->flags & ISAMINIMA)
base = p; base = p;
@ -705,7 +705,7 @@ CKTpzRunTrial(CKTcircuit *ckt, PZtrial **new_trialp, PZtrial **set)
} }
} }
if ((error == E_SINGULAR || new_trial->f_raw.real == 0.0)
if (error == E_SINGULAR || new_trial->f_raw.real == 0.0
&& new_trial->f_raw.imag == 0.0) { && new_trial->f_raw.imag == 0.0) {
new_trial->f_raw.real = 0.0; new_trial->f_raw.real = 0.0;
new_trial->f_raw.imag = 0.0; new_trial->f_raw.imag = 0.0;
@ -941,8 +941,8 @@ CKTpzUpdateSet(PZtrial **set, PZtrial *new)
set[0] = new; set[0] = new;
this_move = FAR_LEFT; this_move = FAR_LEFT;
} else if (new->s.real < set[1]->s.real) { } else if (new->s.real < set[1]->s.real) {
if ((!CKTpzTrapped || new->mag_def < set[1]->mag_def
|| new->mag_def == set[1]->mag_def)
if (!CKTpzTrapped || new->mag_def < set[1]->mag_def
|| new->mag_def == set[1]->mag_def
&& fabs(new->f_def.real) < fabs(set[1]->f_def.real)) { && fabs(new->f_def.real) < fabs(set[1]->f_def.real)) {
/* Really should check signs, not just compare fabs( ) */ /* Really should check signs, not just compare fabs( ) */
set[2] = set[1]; /* XXX = set[2]->prev :: possible opt */ set[2] = set[1]; /* XXX = set[2]->prev :: possible opt */
@ -953,8 +953,8 @@ CKTpzUpdateSet(PZtrial **set, PZtrial *new)
this_move = NEAR_LEFT; this_move = NEAR_LEFT;
} }
} else if (new->s.real < set[2]->s.real) { } else if (new->s.real < set[2]->s.real) {
if ((!CKTpzTrapped || new->mag_def < set[1]->mag_def
|| new->mag_def == set[1]->mag_def)
if (!CKTpzTrapped || new->mag_def < set[1]->mag_def
|| new->mag_def == set[1]->mag_def
&& fabs(new->f_def.real) < fabs(set[1]->f_def.real)) { && fabs(new->f_def.real) < fabs(set[1]->f_def.real)) {
/* Really should check signs, not just compare fabs( ) */ /* Really should check signs, not just compare fabs( ) */
set[0] = set[1]; set[0] = set[1];

69
tests/polezero/filt_bridge_t.out
View File

@ -3,3 +3,72 @@ Circuit: BRIDGE-T FILTER
Circuit: BRIDGE-T FILTER Circuit: BRIDGE-T FILTER
Operating point information:
Node Voltage
---- -------
V(3) 1.200000e+01
V(2) 0.000000e+00
V(1) 1.200000e+01
Source Current
------ -------
v1#branch 0.000000e+00
Capacitor models (Fixed capacitor)
model C
cj 0
cjsw 0
defw 1e-05
narrow 0
Resistor models (Simple linear resistor)
model R
rsh 0
narrow 0
tc1 0
tc2 0
defw 1e-05
Capacitor: Fixed capacitor
device c2 c1
model C C
capacitanc 1e-06 1e-06
i 2.69e-312 2.69e-312
p 2.69e-312 2.69e-312
Resistor: Simple linear resistor
device r4 r3
model R R
resistance 1e+03 1e+03
ac 0 0
i 0 0
p 0 0
Vsource: Independent voltage source
device v1
dc 12
acmag 1
i 0
p -0
BRIDGE-T FILTER
--------------------------------------------------------------------------------
Index pole(1) pole(2)
--------------------------------------------------------------------------------
0 -2.618034e+03, 0.000000e+00 -3.819660e+02, 0.000000e+00
BRIDGE-T FILTER
--------------------------------------------------------------------------------
Index zero(1) zero(2)
--------------------------------------------------------------------------------
0 -1.000000e+03, 0.000000e+00 -1.000000e+03, 0.000000e+00

16
tests/polezero/filt_multistage.out
View File

@ -3,3 +3,19 @@ Circuit: Multistage filter
Circuit: Multistage filter Circuit: Multistage filter
Multistage filter
--------------------------------------------------------------------------------
Index pole(1) pole(2)
--------------------------------------------------------------------------------
0 -5.000000e+10, 0.000000e+00 -8.000000e+08, 0.000000e+00
Multistage filter
--------------------------------------------------------------------------------
Index pole(3)
--------------------------------------------------------------------------------
0 -1.000000e+08, 0.000000e+00

10
tests/polezero/filt_rc.out
View File

@ -3,3 +3,13 @@ Circuit: RC filter
Circuit: RC filter Circuit: RC filter
RC filter
--------------------------------------------------------------------------------
Index all
--------------------------------------------------------------------------------
0 -1.000000e+08, 0.000000e+00
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