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remove Gate.*OverlapCap

pre-master-46
Holger Vogt 8 years ago
committed by rlar
parent
dee9dc370f
commit
9c1b403f79
10 changed files with 15 additions and 129 deletions
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  1. 3
      src/spicelib/devices/vdmos/vdmos.c
  2. 22
      src/spicelib/devices/vdmos/vdmosacld.c
  3. 13
      src/spicelib/devices/vdmos/vdmosask.c
  4. 9
      src/spicelib/devices/vdmos/vdmosdefs.h
  5. 9
      src/spicelib/devices/vdmos/vdmosdset.c
  6. 36
      src/spicelib/devices/vdmos/vdmosload.c
  7. 9
      src/spicelib/devices/vdmos/vdmosmask.c
  8. 12
      src/spicelib/devices/vdmos/vdmosmpar.c
  9. 22
      src/spicelib/devices/vdmos/vdmospzld.c
  10. 9
      src/spicelib/devices/vdmos/vdmosset.c

3
src/spicelib/devices/vdmos/vdmos.c
View File

@ -128,9 +128,6 @@ IFparm VDMOSmPTable[] = { /* model parameters */
IOPA("cbs", VDMOS_MOD_CBS, IF_REAL, "B-S junction capacitance"),
IOP("is", VDMOS_MOD_IS, IF_REAL, "Bulk junction sat. current"),
IOP("pb", VDMOS_MOD_PB, IF_REAL, "Bulk junction potential"),
IOPA("cgso", VDMOS_MOD_CGSO, IF_REAL, "Gate-source overlap cap."),
IOPA("cgdo", VDMOS_MOD_CGDO, IF_REAL, "Gate-drain overlap cap."),
IOPA("cgbo", VDMOS_MOD_CGBO, IF_REAL, "Gate-bulk overlap cap."),
IOP("rsh", VDMOS_MOD_RSH, IF_REAL, "Sheet resistance"),
IOPA("cj", VDMOS_MOD_CJ, IF_REAL, "Bottom junction cap per area"),
IOP("mj", VDMOS_MOD_MJ, IF_REAL, "Bottom grading coefficient"),

22
src/spicelib/devices/vdmos/vdmosacld.c
View File

@ -28,10 +28,6 @@ VDMOSacLoad(GENmodel *inModel, CKTcircuit *ckt)
double capgs;
double capgd;
double capgb;
double GateBulkOverlapCap;
double GateDrainOverlapCap;
double GateSourceOverlapCap;
double EffectiveLength;
for( ; model != NULL; model = VDMOSnextModel(model)) {
for(here = VDMOSinstances(model); here!= NULL;
@ -47,24 +43,12 @@ VDMOSacLoad(GENmodel *inModel, CKTcircuit *ckt)
/*
* meyer's model parameters
*/
EffectiveLength=here->VDMOSl - 2*model->VDMOSlatDiff;
GateSourceOverlapCap = model->VDMOSgateSourceOverlapCapFactor *
here->VDMOSm * here->VDMOSw;
GateDrainOverlapCap = model->VDMOSgateDrainOverlapCapFactor *
here->VDMOSm * here->VDMOSw;
GateBulkOverlapCap = model->VDMOSgateBulkOverlapCapFactor *
here->VDMOSm * EffectiveLength;
capgs = ( *(ckt->CKTstate0+here->VDMOScapgs)+
*(ckt->CKTstate0+here->VDMOScapgs) +
GateSourceOverlapCap );
*(ckt->CKTstate0+here->VDMOScapgs));
capgd = ( *(ckt->CKTstate0+here->VDMOScapgd)+
*(ckt->CKTstate0+here->VDMOScapgd) +
GateDrainOverlapCap );
*(ckt->CKTstate0+here->VDMOScapgd));
capgb = ( *(ckt->CKTstate0+here->VDMOScapgb)+
*(ckt->CKTstate0+here->VDMOScapgb) +
GateBulkOverlapCap );
*(ckt->CKTstate0+here->VDMOScapgb));
xgs = capgs * ckt->CKTomega;
xgd = capgd * ckt->CKTomega;
xgb = capgb * ckt->CKTomega;

13
src/spicelib/devices/vdmos/vdmosask.c
View File

@ -166,10 +166,6 @@ VDMOSask(CKTcircuit *ckt, GENinstance *inst, int which, IFvalue *value,
return(OK);
case VDMOS_CAPGS:
value->rValue = 2* *(ckt->CKTstate0 + here->VDMOScapgs);
/* add overlap capacitance */
value->rValue += (VDMOSmodPtr(here)->VDMOSgateSourceOverlapCapFactor)
* here->VDMOSm
* (here->VDMOSw);
return(OK);
case VDMOS_QGS:
value->rValue = *(ckt->CKTstate0 + here->VDMOSqgs);
@ -179,10 +175,6 @@ VDMOSask(CKTcircuit *ckt, GENinstance *inst, int which, IFvalue *value,
return(OK);
case VDMOS_CAPGD:
value->rValue = 2* *(ckt->CKTstate0 + here->VDMOScapgd);
/* add overlap capacitance */
value->rValue += (VDMOSmodPtr(here)->VDMOSgateDrainOverlapCapFactor)
* here->VDMOSm
* (here->VDMOSw);
return(OK);
case VDMOS_QGD:
value->rValue = *(ckt->CKTstate0 + here->VDMOSqgd);
@ -192,11 +184,6 @@ VDMOSask(CKTcircuit *ckt, GENinstance *inst, int which, IFvalue *value,
return(OK);
case VDMOS_CAPGB:
value->rValue = 2* *(ckt->CKTstate0 + here->VDMOScapgb);
/* add overlap capacitance */
value->rValue += (VDMOSmodPtr(here)->VDMOSgateBulkOverlapCapFactor)
* here->VDMOSm
* (here->VDMOSl
-2*(VDMOSmodPtr(here)->VDMOSlatDiff));
return(OK);
case VDMOS_QGB:
value->rValue = *(ckt->CKTstate0 + here->VDMOSqgb);

9
src/spicelib/devices/vdmos/vdmosdefs.h
View File

@ -308,9 +308,6 @@ typedef struct sVDMOSmodel { /* model structure for a resistor */
double VDMOSgateResistance;
double VDMOSsheetResistance;
double VDMOStransconductance; /* input - use tTransconductance */
double VDMOSgateSourceOverlapCapFactor;
double VDMOSgateDrainOverlapCapFactor;
double VDMOSgateBulkOverlapCapFactor;
double VDMOSoxideCapFactor;
double VDMOSvt0; /* input - use tVto */
double VDMOScapBD; /* input - use tCbd */
@ -345,9 +342,6 @@ typedef struct sVDMOSmodel { /* model structure for a resistor */
unsigned VDMOSgateResistanceGiven :1;
unsigned VDMOSsheetResistanceGiven :1;
unsigned VDMOStransconductanceGiven :1;
unsigned VDMOSgateSourceOverlapCapFactorGiven :1;
unsigned VDMOSgateDrainOverlapCapFactorGiven :1;
unsigned VDMOSgateBulkOverlapCapFactorGiven :1;
unsigned VDMOSvt0Given :1;
unsigned VDMOScapBDGiven :1;
unsigned VDMOScapBSGiven :1;
@ -419,9 +413,6 @@ enum {
VDMOS_MOD_CBS,
VDMOS_MOD_IS,
VDMOS_MOD_PB,
VDMOS_MOD_CGSO,
VDMOS_MOD_CGDO,
VDMOS_MOD_CGBO,
VDMOS_MOD_CJ,
VDMOS_MOD_MJ,
VDMOS_MOD_CJSW,

9
src/spicelib/devices/vdmos/vdmosdset.c
View File

@ -23,9 +23,6 @@ VDMOSdSetup(GENmodel *inModel, CKTcircuit *ckt)
double Beta;
double DrainSatCur;
double EffectiveLength;
double GateBulkOverlapCap;
double GateDrainOverlapCap;
double GateSourceOverlapCap;
double OxideCap;
double SourceSatCur;
double gm;
@ -99,12 +96,6 @@ VDMOSdSetup(GENmodel *inModel, CKTcircuit *ckt)
SourceSatCur = here->VDMOStSatCurDens *
here->VDMOSm * here->VDMOSsourceArea;
}
GateSourceOverlapCap = model->VDMOSgateSourceOverlapCapFactor *
here->VDMOSm * here->VDMOSw;
GateDrainOverlapCap = model->VDMOSgateDrainOverlapCapFactor *
here->VDMOSm * here->VDMOSw;
GateBulkOverlapCap = model->VDMOSgateBulkOverlapCapFactor *
here->VDMOSm * EffectiveLength;
Beta = here->VDMOStTransconductance * here->VDMOSm *
here->VDMOSw/EffectiveLength;
OxideCap = model->VDMOSoxideCapFactor * EffectiveLength *

36
src/spicelib/devices/vdmos/vdmosload.c
View File

@ -25,9 +25,6 @@ VDMOSload(GENmodel *inModel, CKTcircuit *ckt)
double Beta;
double DrainSatCur;
double EffectiveLength;
double GateBulkOverlapCap;
double GateDrainOverlapCap;
double GateSourceOverlapCap;
double SourceSatCur;
double arg;
double cbhat;
@ -117,12 +114,6 @@ VDMOSload(GENmodel *inModel, CKTcircuit *ckt)
SourceSatCur = here->VDMOStSatCurDens *
here->VDMOSm * here->VDMOSsourceArea;
}
GateSourceOverlapCap = model->VDMOSgateSourceOverlapCapFactor *
here->VDMOSm * here->VDMOSw;
GateDrainOverlapCap = model->VDMOSgateDrainOverlapCapFactor *
here->VDMOSm * here->VDMOSw;
GateBulkOverlapCap = model->VDMOSgateBulkOverlapCapFactor *
here->VDMOSm * EffectiveLength;
Beta = here->VDMOStTransconductance * here->VDMOSm *
here->VDMOSw / EffectiveLength;
@ -268,14 +259,11 @@ VDMOSload(GENmodel *inModel, CKTcircuit *ckt)
cdrain = here->VDMOSmode * (here->VDMOScd + here->VDMOScbd);
if (ckt->CKTmode & (MODETRAN | MODETRANOP)) {
capgs = (*(ckt->CKTstate0 + here->VDMOScapgs) +
*(ckt->CKTstate1 + here->VDMOScapgs) +
GateSourceOverlapCap);
*(ckt->CKTstate1 + here->VDMOScapgs));
capgd = (*(ckt->CKTstate0 + here->VDMOScapgd) +
*(ckt->CKTstate1 + here->VDMOScapgd) +
GateDrainOverlapCap);
*(ckt->CKTstate1 + here->VDMOScapgd));
capgb = (*(ckt->CKTstate0 + here->VDMOScapgb) +
*(ckt->CKTstate1 + here->VDMOScapgb) +
GateBulkOverlapCap);
*(ckt->CKTstate1 + here->VDMOScapgb));
}
goto bypass;
@ -702,23 +690,17 @@ VDMOSload(GENmodel *inModel, CKTcircuit *ckt)
vgd1 = vgs1 - *(ckt->CKTstate1 + here->VDMOSvds);
vgb1 = vgs1 - *(ckt->CKTstate1 + here->VDMOSvbs);
if (ckt->CKTmode & (MODETRANOP | MODEINITSMSIG)) {
capgs = 2 * *(ckt->CKTstate0 + here->VDMOScapgs) +
GateSourceOverlapCap;
capgd = 2 * *(ckt->CKTstate0 + here->VDMOScapgd) +
GateDrainOverlapCap;
capgb = 2 * *(ckt->CKTstate0 + here->VDMOScapgb) +
GateBulkOverlapCap;
capgs = 2 * *(ckt->CKTstate0 + here->VDMOScapgs);
capgd = 2 * *(ckt->CKTstate0 + here->VDMOScapgd);
capgb = 2 * *(ckt->CKTstate0 + here->VDMOScapgb);
}
else {
capgs = (*(ckt->CKTstate0 + here->VDMOScapgs) +
*(ckt->CKTstate1 + here->VDMOScapgs) +
GateSourceOverlapCap);
*(ckt->CKTstate1 + here->VDMOScapgs));
capgd = (*(ckt->CKTstate0 + here->VDMOScapgd) +
*(ckt->CKTstate1 + here->VDMOScapgd) +
GateDrainOverlapCap);
*(ckt->CKTstate1 + here->VDMOScapgd));
capgb = (*(ckt->CKTstate0 + here->VDMOScapgb) +
*(ckt->CKTstate1 + here->VDMOScapgb) +
GateBulkOverlapCap);
*(ckt->CKTstate1 + here->VDMOScapgb));
}
/*

9
src/spicelib/devices/vdmos/vdmosmask.c
View File

@ -78,15 +78,6 @@ VDMOSmAsk(CKTcircuit *ckt, GENmodel *inst, int which, IFvalue *value)
case VDMOS_MOD_PB:
value->rValue = model->VDMOSbulkJctPotential;
return(OK);
case VDMOS_MOD_CGSO:
value->rValue = model->VDMOSgateSourceOverlapCapFactor;
return(OK);
case VDMOS_MOD_CGDO:
value->rValue = model->VDMOSgateDrainOverlapCapFactor;
return(OK);
case VDMOS_MOD_CGBO:
value->rValue = model->VDMOSgateBulkOverlapCapFactor;
return(OK);
case VDMOS_MOD_CJ:
value->rValue = model->VDMOSbulkCapFactor;
return(OK);

12
src/spicelib/devices/vdmos/vdmosmpar.c
View File

@ -67,18 +67,6 @@ VDMOSmParam(int param, IFvalue *value, GENmodel *inModel)
model->VDMOSbulkJctPotential = value->rValue;
model->VDMOSbulkJctPotentialGiven = TRUE;
break;
case VDMOS_MOD_CGSO:
model->VDMOSgateSourceOverlapCapFactor = value->rValue;
model->VDMOSgateSourceOverlapCapFactorGiven = TRUE;
break;
case VDMOS_MOD_CGDO:
model->VDMOSgateDrainOverlapCapFactor = value->rValue;
model->VDMOSgateDrainOverlapCapFactorGiven = TRUE;
break;
case VDMOS_MOD_CGBO:
model->VDMOSgateBulkOverlapCapFactor = value->rValue;
model->VDMOSgateBulkOverlapCapFactorGiven = TRUE;
break;
case VDMOS_MOD_CJ:
model->VDMOSbulkCapFactor = value->rValue;
model->VDMOSbulkCapFactorGiven = TRUE;

22
src/spicelib/devices/vdmos/vdmospzld.c
View File

@ -29,10 +29,6 @@ VDMOSpzLoad(GENmodel *inModel, CKTcircuit *ckt, SPcomplex *s)
double capgs;
double capgd;
double capgb;
double GateBulkOverlapCap;
double GateDrainOverlapCap;
double GateSourceOverlapCap;
double EffectiveLength;
for( ; model != NULL; model = VDMOSnextModel(model)) {
for(here = VDMOSinstances(model); here!= NULL;
@ -48,21 +44,9 @@ VDMOSpzLoad(GENmodel *inModel, CKTcircuit *ckt, SPcomplex *s)
/*
* meyer's model parameters
*/
EffectiveLength=here->VDMOSl - 2*model->VDMOSlatDiff;
GateSourceOverlapCap = model->VDMOSgateSourceOverlapCapFactor *
here->VDMOSm * here->VDMOSw;
GateDrainOverlapCap = model->VDMOSgateDrainOverlapCapFactor *
here->VDMOSm * here->VDMOSw;
GateBulkOverlapCap = model->VDMOSgateBulkOverlapCapFactor *
here->VDMOSm * EffectiveLength;
capgs = ( 2* *(ckt->CKTstate0+here->VDMOScapgs)+
GateSourceOverlapCap );
capgd = ( 2* *(ckt->CKTstate0+here->VDMOScapgd)+
GateDrainOverlapCap );
capgb = ( 2* *(ckt->CKTstate0+here->VDMOScapgb)+
GateBulkOverlapCap );
capgs = ( 2* *(ckt->CKTstate0+here->VDMOScapgs));
capgd = ( 2* *(ckt->CKTstate0+here->VDMOScapgd));
capgb = ( 2* *(ckt->CKTstate0+here->VDMOScapgb));
xgs = capgs;
xgd = capgd;
xgb = capgb;

9
src/spicelib/devices/vdmos/vdmosset.c
View File

@ -42,15 +42,6 @@ VDMOSsetup(SMPmatrix *matrix, GENmodel *inModel, CKTcircuit *ckt,
if (!model->VDMOStransconductanceGiven) {
model->VDMOStransconductance = 2e-5;
}
if (!model->VDMOSgateSourceOverlapCapFactorGiven) {
model->VDMOSgateSourceOverlapCapFactor = 0;
}
if (!model->VDMOSgateDrainOverlapCapFactorGiven) {
model->VDMOSgateDrainOverlapCapFactor = 0;
}
if (!model->VDMOSgateBulkOverlapCapFactorGiven) {
model->VDMOSgateBulkOverlapCapFactor = 0;
}
if (!model->VDMOSvt0Given) {
model->VDMOSvt0 = 0;
}

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