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Handle the case when control voltages on and off are equal.
Handle the case when control voltages on and off are equal.
Update the linear switch: add the limits to resistance ron, roff Update the log switch: correct the resistance calculation for von < voff Add some examples for the pswitch.pre-master-46
3 changed files with 180 additions and 42 deletions
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52examples/xspice/vswitch-test-lin.cir
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52examples/xspice/vswitch-test-log.cir
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118src/xspice/icm/xtradev/pswitch/cfunc.mod
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* sw ring-oscillators |
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.control |
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destroy all |
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run |
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plot I(vmeasurea) I(vmeasureb) I(vmeasurec) I(vmeasured) |
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plot V(outa) V(outb) V(outc) V(outd) |
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rusage |
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.endc |
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.tran 3m 3 |
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VDD VDD2 0 DC 3 |
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Rla VDD2 outa 1k |
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Rlb VDD2 outb 1k |
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Rlc VDD2 outc 1k |
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Rld VDD2 outd 1k |
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VMEASUREa DGNDa 0 dc 0 |
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VMEASUREb DGNDb 0 dc 0 |
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VMEASUREc DGNDc 0 dc 0 |
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VMEASUREd DGNDd 0 dc 0 |
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Vin in 0 pulse ( 0 3 0 3 3 10 10 ) |
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xsa in outa DGNDa switcha |
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xsb in outb DGNDb switchb |
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xsc in outc DGNDc switchc |
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xsd in outd DGNDd switchd |
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.subckt switcha In Out DGND |
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a.xx17.asn %gd in DGND %gd out DGND aswswitch |
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.model aswswitch pswitch( log=false cntl_on=1.5 cntl_off=2.5 r_on=1k r_off=2g) |
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.ends |
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.subckt switchb In Out DGND |
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a.xx17.asn %gd in DGND %gd out DGND aswswitch |
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.model aswswitch pswitch( log=false cntl_on=1.5 cntl_off=2.5 r_on=1k r_off=2k) |
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.ends |
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.subckt switchc In Out DGND |
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a.xx17.asn %gd in DGND %gd out DGND aswswitch |
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.model aswswitch pswitch( log=false cntl_on=2.5 cntl_off=1.5 r_on=1k r_off=2g) |
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.ends |
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.subckt switchd In Out DGND |
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a.xx17.asn %gd in DGND %gd out DGND aswswitch |
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.model aswswitch pswitch( log=false cntl_on=2.5 cntl_off=1.5 r_on=1k r_off=2k) |
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.ends |
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.end |
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* sw ring-oscillators |
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.control |
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destroy all |
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run |
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plot I(vmeasurea) I(vmeasureb) I(vmeasurec) I(vmeasured) |
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plot V(outa) V(outb) V(outc) V(outd) |
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rusage |
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.endc |
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.tran 3m 3 |
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VDD VDD2 0 DC 3 |
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Rla VDD2 outa 1k |
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Rlb VDD2 outb 1k |
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Rlc VDD2 outc 1k |
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Rld VDD2 outd 1k |
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VMEASUREa DGNDa 0 dc 0 |
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VMEASUREb DGNDb 0 dc 0 |
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VMEASUREc DGNDc 0 dc 0 |
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VMEASUREd DGNDd 0 dc 0 |
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Vin in 0 pulse ( 0 3 0 3 3 10 10 ) |
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xsa in outa DGNDa switcha |
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xsb in outb DGNDb switchb |
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xsc in outc DGNDc switchc |
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xsd in outd DGNDd switchd |
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.subckt switcha In Out DGND |
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a.xx17.asn %gd in DGND %gd out DGND aswswitch |
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.model aswswitch pswitch( log=true cntl_on=1.5 cntl_off=2.5 r_on=1k r_off=2g) |
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.ends |
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.subckt switchb In Out DGND |
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a.xx17.asn %gd in DGND %gd out DGND aswswitch |
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.model aswswitch pswitch( log=true cntl_on=1.5 cntl_off=2.5 r_on=1k r_off=2k) |
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.ends |
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.subckt switchc In Out DGND |
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a.xx17.asn %gd in DGND %gd out DGND aswswitch |
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.model aswswitch pswitch( log=true cntl_on=2.5 cntl_off=1.5 r_on=1k r_off=2g) |
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.ends |
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.subckt switchd In Out DGND |
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a.xx17.asn %gd in DGND %gd out DGND aswswitch |
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.model aswswitch pswitch( log=true cntl_on=2.5 cntl_off=1.5 r_on=1k r_off=2k) |
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.ends |
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.end |
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