From f1d0d407536f865f12ad9a84a426d784e3325c32 Mon Sep 17 00:00:00 2001 From: h_vogt Date: Tue, 7 Aug 2012 23:11:52 +0200 Subject: [PATCH] demonstrate effect of W crossing binning limits --- examples/measure/mos-meas-dc-control.sp | 36 +++++++++++++++---------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/examples/measure/mos-meas-dc-control.sp b/examples/measure/mos-meas-dc-control.sp index f67494215..9869cf602 100644 --- a/examples/measure/mos-meas-dc-control.sp +++ b/examples/measure/mos-meas-dc-control.sp @@ -1,5 +1,8 @@ ***** Single NMOS Transistor .measure (Id-Vd) *** -m1 d g s b nch L=0.6u W=9.0u +* Altering device witdth leads to select new model due to binning limits. +* New model has artificially thick gate oxide (changed from default 3n to 4n) +* to demonstrate the effect. +m1 d g s b nch L=0.6u W=9.99u ; W is slightly below binning limit vgs g 0 3.5 vds d 0 3.5 @@ -7,27 +10,32 @@ vs s 0 dc 0 vb b 0 dc 0 * model binning -.model nch.1 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) -.model nch.2 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u ) -.model pch.1 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) -.model pch.2 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u ) +* uses default parameters, except toxe +.model nch.1 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u toxe=3n ) +.model nch.2 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u toxe=4n) .control -dc vds 0 3.5 0.05 vgs 0.5 3.5 0.5 +dc vds 0 3.5 0.05 vgs 3.5 0.5 -0.5 meas dc is_at FIND i(vs) AT=1 -meas dc is_max max i(vs) from=0 to=3.5 +meas dc is_max max i(vs) meas dc vds_at2 when i(vs)=10m +* starting with branches in descending order of vgs +* trig ist the first branch which crosses 5mA +* Targ is the first branch crossing 10mA meas dc vd_diff1 trig i(vs) val=0.005 rise=1 targ i(vs) val=0.01 rise=1 -meas dc vd_diff2 trig i(vs) val=0.005 rise=1 targ i(vs) val=0.01 rise=2 -*rusage all -*plot i(vs) -alter @m1[w]=11u -dc vds 0 3.5 0.05 vgs 0.5 3.5 0.5 +* trig ist the first branch which crosses 5mA +* Targ is the second branch crossing 10mA +meas dc vd_diff2 trig i(vs) val=0.005 rise=2 targ i(vs) val=0.01 rise=2 +alter @m1[w]=10.01u ; W is slightly above binning limit +dc vds 0 3.5 0.05 vgs 3.5 0.5 -0.5 meas dc is_at FIND i(vs) AT=1 -meas dc is_max max i(vs) from=0 to=3.5 +meas dc is_max max i(vs) meas dc vds_at2 when i(vs)=10m meas dc vd_diff1 trig i(vs) val=0.005 rise=1 targ i(vs) val=0.01 rise=1 -meas dc vd_diff2 trig i(vs) val=0.005 rise=1 targ i(vs) val=0.01 rise=2 +* there is only one branch crossing 10mA, so this second meas fails with targ out of interval +echo +echo The next one will fail (no two branches crossing 10 mA): +meas dc vd_diff2 trig i(vs) val=0.005 rise=2 targ i(vs) val=0.01 rise=2 *rusage all plot dc1.i(vs) i(vs) .endc