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Fix another error in 9c71db3a72.

pre-master-46
Giles Atkinson 3 years ago
committed by Holger Vogt
parent
commit
f4f2f41940
  1. 1
      src/spicelib/devices/vsrc/vsrcload.c

1
src/spicelib/devices/vsrc/vsrcload.c

@ -319,6 +319,7 @@ VSRCload(GENmodel *inModel, CKTcircuit *ckt)
period = end_time -
here->VSRCcoeffs[here->VSRCrBreakpt];
time -= period * floor(time / period);
time += here->VSRCcoeffs[here->VSRCrBreakpt];
} else {
value =
here->VSRCcoeffs[here->VSRCfunctionOrder - 1];

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