3d6d0d880a
Improve comment
1 year ago
27db91480b
Fix bug no. 708, reported by Philip Sauvage.
1 year ago
16798edb36
Minor change.
2 years ago
5f8ab0eb67
Minor change.
2 years ago
9d2e2f77c0
Minor change.
2 years ago
b40dcaa18d
OpenVAF-reloaded compiled model support.
2 years ago
368c59466b
Allow plotting a single point in an ascii plot
(command .asciiplot)
1 year ago
e3f7cf3e0a
Fix Bug #698 -
"Initial transient solution assumes voltage source=0 even if it is not."
Cause was another error in ad5bb9eb8d#607 , which uncovered
an earlier latent bug.
1 year ago
537d55d80b
Improve an error message.
1 year ago
cf812da363
Try to clarify the mechanism of parameter substitution and add
an example of substituting an XSPICE vector parameter.
1 year ago
e130371410
Added: Error: Pole/zero analysis is not (yet) supported with 'option KLU'.
Use 'option sparse' instead.
1 year ago
09d352be12
This does not fix noise analysis with klu.
It does add missing { and } when event-driven instances are not present.
Without this change CKTop will always be called again directly in NOISEan even
if CKTop was previously called by EVTop. This matches the intended
behavior before #ifdef KLU was added.
2 years ago
b350786c48
Some cosmetics
1 year ago
bafa3ff8a3
Revert the sign of ac_gain.real
Fix bug no 697, reported by Matthieu Guerquin-Kern
1 year ago
0fadbdc488
Don't compile with OpenMP support, as it is not used in KLU.
1 year ago
2d9e5fede6
/openmp:llvm removed from additional options for the 'Release' builds
(however keep it in the 'ReleaseOMP' builds).
1 year ago
f300154922
Insert correct conversion sections for KLU matrices
2 years ago
c8959ba072
ignore visualc xspice verilog dir
2 years ago
2129ac26fd
Add optional series resistance or junction capacitance, if non
is defined in the .model statement. This may help achieving
convergence if subcircut models of opamps etc use simple diodes
as voltage limiters. Example call:
.options diode_cj0=20p diode_rser=20m
2 years ago
d5f0c6598f
Fix commit 09685dde1
("Set lower case for variables or vectors in command 'echo'.
Tokens starting with '$' will get lower-casing.", 2024-09-07)
Don't use s as name for temporary string, as s has been set
already and is used later.
2 years ago
b62528d7e5
Set lower case for variables or vectors in command 'echo'.
Tokens starting with '$' will get lower-casing.
2 years ago
82af46085d
Enable using fftw3 as a build option of shared ngspice on Windows
2 years ago
d425d38c44
Old deprecated ADMS examples removed.
2 years ago
419e821a09
Fixed KLU conversion to complex for SP Analysis
2 years ago
287280c3db
Make error messages more verbose:
add line number and source file name.
2 years ago
bce621680b
Add line number and source file to some error messages
2 years ago
8e8716abc7
Fix warning message
2 years ago
c2c35b56a4
More on verbose error and warning messages
2 years ago
4e6af5a55f
Allow KiCad special token V(/xyz) by quoting
2 years ago
c33fd66a21
Make error messages more verbose:
add line number and source file name.
2 years ago
3528156d14
Fix bug #680 . Check that src/dest memcpy arguments are non-NULL.
2 years ago
4e318c7a23
no built-in model for bsimbulk, so no qa test needed
2 years ago
8fbd357fdd
extend bsim4 operating point info list
2 years ago
123ed0aada
Add simulator version info to raw file ('write' commad)
using an extra line 'Command: ...').
The old sequence (adding commands manually to raw file) is
still available.
The 'Command: anycommand' will not be executed if loading
an ngspice-generated raw file. Raw files from other simulators may
generate a warning that the command is not available.
2 years ago
1087c6a0c2
Add simulator version info to raw file in batch mode,
using the line 'Command:...'
2 years ago
14844af175
Fix #686 : "XSpice Verilog Vector Input Bug".
Bug report and fix by Aodhan Murray.
2 years ago
5f059abdca
Improve debugging using shared ngspice:
print out each command received.
2 years ago
f495431509
Add a comment
2 years ago
a96237061d
Copy the correct spinit to ngspice/visualc
2 years ago
9e571d7df1
git ignore vcd files
2 years ago
984cd9cc10
extend unwanted output list
2 years ago
4cffcd96ce
add missing klu bindings
2 years ago
606c6d0df7
Notes go to stdout.
2 years ago
232101af10
Don't dereference a NULL pointer.
2 years ago
501a64470f
Error and warning messages to stderr
2 years ago
34549c4524
Note directed to stdout
2 years ago
4a1698c22d
enable compiling with CYGWIN
2 years ago
f4c7202130
Fix gcc warnings.
2 years ago
35968d1da6
Add additional examples of Verilog co-simulation and share the Verilog
source and large parts of the example circuits between Verilator and
Icarus Verilog. Verilog source file adc.v has improved style:
all assignments in the always block are now non-blocking.
2 years ago
64a9a0bfbc
Add a utility function to the d_cosim code model to open dynamic
libraries. It automatically tries adding standard file extensions,
so that model lines for d_cosim can be the same for all OSs.
2 years ago
Holger Vogt
Árpád Bűrmen
Giles Atkinson
Brian Taylor
Alessio Cacciatori
dwarning
Francesco Lannutti
Vogt