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1 Commits (d5ef8a366033604d349a3e5a4a3b5e9c8f69c0ea)

Author	SHA1	Message	Date
Giles Atkinson	35968d1da6	Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.	2 years ago
Giles Atkinson	c18447f9f5	Add the support files for co-simulation with Verilog code compiled by Verilator. Also add script files to Visual Studio builds that are already installed by the Makefile builds.	2 years ago