Tree: dcb4202910

pre-master-46

Branches Tags

${ item.name }

Create tag ${ searchTerm }

Create branch ${ searchTerm }

from 'dcb4202910'

${ noResults }

Commit Graph

3 Commits (dcb420291004ee069ac8ba052d14e4e1d460e43c)

Author	SHA1	Message	Date
Giles Atkinson	fd3827af40	Fix ordering of parameter definition and use. Icarus Verilog no longer accepts use-before-definition. Also slightly expand the README for Icarus Verilog examples.	1 year ago
Giles Atkinson	35968d1da6	Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.	2 years ago
Giles Atkinson	c18447f9f5	Add the support files for co-simulation with Verilog code compiled by Verilator. Also add script files to Visual Studio builds that are already installed by the Makefile builds.	2 years ago