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53 lines
1.3 KiB
53 lines
1.3 KiB
4 BIT ALL-NAND-GATE BINARY ADDER with node names 能 and せん
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not yet supported!
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.param W咦 = 3u
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*** SUBCIRCUIT DEFINITIONS
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.SUBCKT NAдND 能 せん out VDD
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* NODES: INPUT(2), OUTPUT, VCC
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M1 out せん Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p
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M2 net.1 せん 0 0 n1 W='W咦' L=0.35u pd=9u ad=9p ps=9u as=9p
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M3 out 能 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p
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M4 out 能 net.1 0 n1 W='W咦' L=0.35u pd=9u ad=9p ps=9u as=9p
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.ENDS NAдND
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X않1 1 は2 7 99 NAдND
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*** POWER
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V을을 99 0 DC 3.3V
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*** ALL INPUTS
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VIN1A 1 0 DC 0 PULSE(0 3 0 5NS 5NS 20NS 50NS)
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VIN1B は2 0 DC 0 PULSE(0 3 0 5NS 5NS 30NS 100NS)
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.option noinit acct
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.TRAN 500p 6400NS
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* save inputs
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.save V(1) V(は2) V(7)
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* use BSIM3 model with default parameters
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.model n1 nmos level=49 version=3.3.0
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.model p1 pmos level=49 version=3.3.0
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*.include ./Modelcards/modelcard32.nmos
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*.include ./Modelcards/modelcard32.pmos
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.control
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* for CYGWIN
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setcs xfont='Noto Sans CJK JP Medium'
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set xfont_size=16
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if $?batchmode
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else
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pre_set strict_errorhandling
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unset ngdebug
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*save outputs and specials
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run
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display
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* plot the inputs and outputs, use offset to plot on top of each other
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let れ1 = 4
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let れ2 = 8
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plot v(1) v(は2)+れ1 v(7)+れ2
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endif
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.endc
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.END
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