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pyNgSpice/examples/digital/digital_devices
Brian Taylor 09f070f582
Error handling improvements in cfunc.mod. Ensure that d_process.h wiil always respond to version and interface checks sent from sendheader. This is needed so that the pipe reads in sendheader do not cause Windows to hang when the interface version and in/out counts do not match. This hang was the cause of errors not being reported and the Windows gui hanging. Startup and header checks are now detected in cm_d_process, and the simulator will run but with runtime errors since a d_process model cannot be completely instantiated after initial errors. It would be good to find a means of gracefully halting the simulation run. 		2 years ago
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.spiceinit Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file. 3 years ago
74f524-cp.stim Add serial load to 74f524 example. 3 years ago
74f524-csi.stim Add serial load to 74f524 example. 3 years ago
74f524-io.stim Add serial load to 74f524 example. 3 years ago
74f524-s0s1.stim Add serial load to 74f524 example. 3 years ago
74f524-sem.stim Add serial load to 74f524 example. 3 years ago
74f524.cir Add serial load to 74f524 example. 3 years ago
7490a.cir Example for 7490a Pspice subckt. This exercises jkff, logicexp, and pindly conversions to XSPICE. 3 years ago
7490a.clk.stim Example for 7490a Pspice subckt. This exercises jkff, logicexp, and pindly conversions to XSPICE. 3 years ago
7490a.control.stim Example for 7490a Pspice subckt. This exercises jkff, logicexp, and pindly conversions to XSPICE. 3 years ago
behav-283-1.cir Move digital examples to new locations 3 years ago
behav-283-1.stim Move digital examples to new locations 3 years ago
behav-283.cir Move digital examples to new locations 3 years ago
behav-568.cir Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file. 3 years ago
behav-568.stim Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file. 3 years ago
behav-tristate-pulse.cir Move digital examples to new locations 3 years ago
behav-tristate-pulse.stim Move digital examples to new locations 3 years ago
behav-tristate.cir Move digital examples to new locations 3 years ago
behav-tristate.stim Move digital examples to new locations 3 years ago
counter.cir Move digital examples to new locations 3 years ago
decoder.cir Move digital examples to new locations 3 years ago
decoder.stim Move digital examples to new locations 3 years ago
ex4.cir Move digital examples to new locations 3 years ago
ex4.stim Move digital examples to new locations 3 years ago
ex5.cir Use ~ on the input of a tristate buffer for INV3, and avoid creating an extra inverter. For ff/latch use ~ on set/reset and jkff clock inputs to avoid creating extra inverters. 3 years ago
ex5.stim Move digital examples to new locations 3 years ago
ex283.cir Move digital examples to new locations 3 years ago
ex283.stim Move digital examples to new locations 3 years ago
nggtk.tcl Move digital examples to new locations 3 years ago
xspice_c4.cir Move digital examples to new locations 3 years ago