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pyNgSpice/tests/bsim1

History

dwarning 17497eddec VDMOS change thermal left and rigth side signs that mos and diode part follow same logic		6 years ago
..
Makefile.am	whitespace cleanup (all Makefile.am files)	16 years ago
test.cir	.options NOACCT	17 years ago
test.out	Added test structure for bsim1.	23 years ago