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pyNgSpice/examples/vbic

History

dwarning 2afbcfd070 The HICUM Level0 Bipolar Model in Verilog-A (Original Version 1.1 - only VT0 changed to Vt0)		20 years ago
..
CEamp.sp	Added some examples.	22 years ago
FG.sp	Added some examples.	22 years ago
FO.sp	Added some examples.	22 years ago
diffamp.sp	Added some examples.	22 years ago
diode.sp	Added some examples.	22 years ago
noise_scale_test.sp	Added some examples.	22 years ago
temp.sp	Added some examples.	22 years ago
tran_aplac_test.sp	Added some examples.	22 years ago
vbic.sp	Added some examples.	22 years ago