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pyNgSpice/visualc/ng_shared_xspice_v/ng_shared_test_v

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Giles Atkinson 35968d1da6 Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.		2 years ago
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ng_shared_test_v.vcxproj	Squashed commit of the following:	5 years ago