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pyNgSpice/tests/hisim

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Brian Taylor 4111aaf110 When logicexp has a ugate timing model other than d0_gate, use its delays for an inverter or buffer.		3 years ago
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nmos	model qa check for other simulator	11 years ago
pmos	model qa check for other simulator	11 years ago
Makefile.am	remove test1.cir from EXTRA_DIST	15 years ago