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pyNgSpice/examples/xspice

History

Giles Atkinson 35968d1da6 Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.		2 years ago
..
d_lut	Obtain memory and simulation time	4 years ago
d_process	Add notes on the structure and organization of an external d_process program.	2 years ago
d_source	Fixed KLU conversion to complex for SP Analysis	1 year ago
delay	Obtain memory and simulation time	4 years ago
delta-sigma	Fixed KLU conversion to complex for SP Analysis	1 year ago
filesource	Fixed KLU conversion to complex for SP Analysis	1 year ago
icarus_verilog	Fixed KLU conversion to complex for SP Analysis	1 year ago
original-examples	Add null-pointer checks to some code that crashed when trying	2 years ago
pll	Fixed KLU conversion to complex for SP Analysis	1 year ago
pwm-osc	Examples for d_pwm and d_osc	3 years ago
state	Obtain memory and simulation time	4 years ago
table	Fixed KLU conversion to complex for SP Analysis	1 year ago
various	Various filter examples using Laplace expression x_fer	3 years ago
verilator	Add additional examples of Verilog co-simulation and share the Verilog	1 year ago