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pyNgSpice/src/ciderlib

History

Holger Vogt c05a6398b7 Reserve enough memory		1 year ago
..
input	Add EXITPOINTs, if reading inputs etc. fails	6 years ago
oned	Reserve enough memory	1 year ago
support	Replace all BOOLEAN, BOOL, _Bool by bool	1 year ago
twod	Reserve enough memory	1 year ago
Makefile.am	Cider simulator (simulator routines) Import.	23 years ago
notes	Cider simulator (simulator routines) Import.	23 years ago