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pyNgSpice/tests/bsim3/pmos/reference

History

Brian Taylor b142be7fde Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE.		3 years ago
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acFreq.standard	introduce the more reliable cmc quality check for bsim3 model	12 years ago
acFreq_acnqsmod.standard	introduce the more reliable cmc quality check for bsim3 model	12 years ago
acFreq_capmod.standard	introduce the more reliable cmc quality check for bsim3 model	12 years ago
acFreq_mobmod.standard	introduce the more reliable cmc quality check for bsim3 model	12 years ago
acFreq_xpart.standard	introduce the more reliable cmc quality check for bsim3 model	12 years ago
acVd.standard	introduce the more reliable cmc quality check for bsim3 model	12 years ago
dcSweep_lw1.standard	introduce the more reliable cmc quality check for bsim3 model	12 years ago
dcSweep_lw1_vb1.standard	introduce the more reliable cmc quality check for bsim3 model	12 years ago
dcSweep_lw2.standard	introduce the more reliable cmc quality check for bsim3 model	12 years ago
dcSweep_lw3.standard	introduce the more reliable cmc quality check for bsim3 model	12 years ago
dcSweep_lw4.standard	introduce the more reliable cmc quality check for bsim3 model	12 years ago
dcSweep_nrd_nrs.standard	introduce the more reliable cmc quality check for bsim3 model	12 years ago
noise1.standard	introduce the more reliable cmc quality check for bsim3 model	12 years ago
noise2.standard	introduce the more reliable cmc quality check for bsim3 model	12 years ago