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pyNgSpice/examples/TransmissionLines
Holger Vogt b8357edddc
Add analog code model astate. 		6 months ago
..
URC-TM-SUB.cir Example for URC distributed RC transmission line 3 years ago
cpl1_4_line.sp Hopefully more meaningful transmissionline examples 16 years ago
cpl2_2_line.sp Hopefully more meaningful transmissionline examples 16 years ago
cpl3_4_line.sp Hopefully more meaningful transmissionline examples 16 years ago
cpl4_txl_2_line.sp txl model needs g value 16 years ago
cpl_ibm1.sp fix the c matrix unsymmetry 16 years ago
cpl_ibm1a.sp Update to Garbage Collector for cpl 4 years ago
cpl_ibm2.sp matrixes must be complete to prevent access violation 16 years ago
cpl_ibm3.sp suppress a warning by inserting the default diode model 12 years ago
ltra1_1_line.sp Better visibility of the results 3 years ago
ltra1_4_line.sp Better visibility of the results 3 years ago
ltra2_2_line.sp Better visibility of the results 3 years ago
ltra3_2_line.sp Better visibility of the results 3 years ago
ltra4_1_line.sp Better visibility of the results 3 years ago
ltra5_1_line.sp Better visibility of the results 3 years ago
ltra6_2_line.sp Better visibility of the results 3 years ago
ltra7_4_line.sp Better visibility of the results 3 years ago
txl1_1_line.sp Hopefully more meaningful transmissionline examples 16 years ago
txl2_3_line.sp Hopefully more meaningful transmissionline examples 16 years ago
txl3_1_line.sp big kspice model update 16 years ago
txl4_1_line.sp Remove double defined xrcv 5 years ago