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pyNgSpice/examples/cider

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Brian Taylor 57dd3342ef Enable CIDER with KLU for DC, OP, and TRAN analyses. Small signal AC analysis is not yet supported for CIDER complex valued device KLU matrices. The examples/cider testcases produce printed simulation result values which have slight differences between Sparse and KLU. Differences are probably expected and in a few cases are ~1-2%, sometimes a little more. This should be good enough for most CIDER analyses. Francesco did a good piece of work. Runtimes are significantly shorter with KLU.		7 months ago
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bicmos	Add analog code model astate.	6 months ago
bjt	Add analog code model astate.	6 months ago
cider-gnuplot	Add analog code model astate.	6 months ago
diode	Add analog code model astate.	6 months ago
jfet	Add analog code model astate.	6 months ago
mos	Add analog code model astate.	6 months ago
parallel	Add analog code model astate.	6 months ago
resistor	Add analog code model astate.	6 months ago
serial	Add analog code model astate.	6 months ago
surfmob	Add analog code model astate.	6 months ago