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pyNgSpice/examples/xspice

History

Giles Atkinson 35968d1da6 Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.		2 years ago
..
d_lut	Obtain memory and simulation time	4 years ago
d_process	Try to clarify the mechanism of parameter substitution and add	1 year ago
d_source	Obtain memory and simulation time	4 years ago
delay	Try to clarify the mechanism of parameter substitution and add	1 year ago
delta-sigma	add y-axis label	4 years ago
filesource	Obtain memory and simulation time	4 years ago
icarus_verilog	Add additional examples of Verilog co-simulation and share the Verilog	1 year ago
original-examples	Try to clarify the mechanism of parameter substitution and add	1 year ago
pll	Add an option to the iplot command: -d sets the number of simulation	3 years ago
pwm-osc	Try to clarify the mechanism of parameter substitution and add	1 year ago
state	Obtain memory and simulation time	4 years ago
table	New tables for MOS devices	4 years ago
various	Try to clarify the mechanism of parameter substitution and add	1 year ago
verilator	Try to clarify the mechanism of parameter substitution and add	1 year ago