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pyNgSpice/examples/osdi/bsimcmg

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Brian Taylor f570b04d6c For unspecified gate delays (logic and tristate gates), which PSpice would consider as zero, set the rise and fall delays to 1.e-12s (the minimum for Xspice). For dff, jkff, dlatch, and srlatch use the Xspice default 1.0ns for rise and fall delays. If the ngspice variable (ps_port_directions & 2) is true, write the translated subckt to stdout, with TRANS_OUT prefix, for debugging purposes. The user could edit and replace the translated subckt if desired.		3 years ago
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Modelcards	Update to the examples for osdi	3 years ago
inverter_ro.sp	Update the example structure for OSDI/OpenVAF:	3 years ago
inverter_transient.sp	Update the example structure for OSDI/OpenVAF:	3 years ago
netlist_nmos.sp	Update the example structure for OSDI/OpenVAF:	3 years ago
netlist_pmos.sp	Update the example structure for OSDI/OpenVAF:	3 years ago
ringosc_17stg.sp	Update the example structure for OSDI/OpenVAF:	3 years ago
simple_inverter_dc.sp	Update the example structure for OSDI/OpenVAF:	3 years ago