Fix Bug #630 - "pwl if r=last time, simulation never ends".

Allowing a PWL repeat to start at the last time-point makes no sense.

src/spicelib/devices/vsrc/vsrcpar.c

@@ -140,7 +140,7 @@ VSRCparam(int param, IFvalue *value, GENinstance *inst, IFvalue *select)
             }
 
             end_time     = *(here->VSRCcoeffs + here->VSRCfunctionOrder-2);
-            if ( here->VSRCr > end_time ) {
+            if ( here->VSRCr >= end_time ) {
               fprintf(stderr, "ERROR: repeat start time value %g for pwl voltage source must be smaller than final time point given!\n", here->VSRCr );
               return ( E_PARMVAL );
             }