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@ -6,6 +6,7 @@ |
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# |
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# Rel Date Who Comments |
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# ==== ========== ============= ======== |
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# 1.2 04/15/2024 Geoffrey Coram Support op-pt values |
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# 1.1 07/05/17 Dietmar Warning Version detection included |
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# 1.0 05/13/11 Dietmar Warning Initial version |
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# |
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@ -88,7 +89,7 @@ sub runNoiseTest { |
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print OF "rin dummy 0 1.0 noise=0"; |
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foreach $pin (@main::Pin) { |
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if ($main::isFloatingPin{$pin}) { |
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print OF "i_$pin $pin 0 0"; |
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print OF "r_$pin $pin 0 1e15"; |
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} elsif ($pin eq $main::biasListPin) { |
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print OF "v_$pin $pin 0 $biasVoltage"; |
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} elsif ($pin eq $main::biasSweepPin) { |
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@ -206,6 +207,7 @@ sub runAcTest { |
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print OF "* AC simulation for $main::simulatorName"; |
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&generateCommonNetlistInfo($variant,$temperature); |
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foreach $fPin (@main::Pin) { |
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next if (!$main::needAcStimulusFor{$fPin}); |
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foreach $mPin (@main::Pin) { |
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if ($mPin eq $fPin) { |
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$acStim=" ac 1"; |
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@ -213,7 +215,7 @@ sub runAcTest { |
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$acStim=""; |
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} |
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if ($main::isFloatingPin{$mPin}) { |
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print OF "i_${mPin}_$fPin ${mPin}_$fPin 0 0"; |
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print OF "r_${mPin}_$fPin ${mPin}_$fPin 0 1e15"; |
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} elsif ($mPin eq $main::biasListPin) { |
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print OF "v_${mPin}_$fPin ${mPin}_$fPin 0 $biasVoltage$acStim"; |
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} elsif ($mPin eq $main::biasSweepPin) { |
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@ -226,7 +228,9 @@ sub runAcTest { |
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} |
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print OF ".ac $main::frequencySpec"; |
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foreach $mPin (@main::Pin) { |
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next if (!$main::needAcStimulusFor{$mPin}); |
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foreach $fPin (@main::Pin) { |
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next if (!$main::needAcStimulusFor{$fPin}); |
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print OF ".print ac i(v_${mPin}_$fPin)"; |
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} |
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} |
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@ -349,7 +353,7 @@ sub runDcTest { |
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&generateCommonNetlistInfo($variant,$temperature); |
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foreach $pin (@main::Pin) { |
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if ($main::isFloatingPin{$pin}) { |
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print OF "i_$pin $pin 0 0"; |
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print OF "r_$pin $pin 0 1e15"; |
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} elsif ($pin eq $main::biasListPin) { |
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print OF "v_$pin $pin 0 $biasVoltage"; |
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} elsif ($pin eq $main::biasSweepPin) { |
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@ -361,7 +365,9 @@ sub runDcTest { |
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print OF "x1 ".join(" ",@main::Pin)." mysub"; |
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print OF ".dc v_$main::biasSweepPin $main::biasSweepSpec"; |
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foreach $pin (@main::Outputs) { |
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if ($main::isFloatingPin{$pin}) { |
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if ($pin =~ /^OP\((.*)\)/) { |
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print OF ".print dc \@${main::keyLetter}.x1.${main::keyLetter}1[$1]"; |
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} elsif ($main::isFloatingPin{$pin}) { |
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print OF ".print dc v($pin)"; |
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} else { |
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print OF ".print dc i(v_$pin)"; |
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@ -381,6 +387,7 @@ sub runDcTest { |
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while (<SIMULATE>) { |
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chomp;s/^\s+//;s/\s+$//;s/#branch//;s/\(/_/;s/\)//; |
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if (/^Index\s+v-sweep\s+v_/i) {$inResults=1;($pin=$');<SIMULATE>;next} |
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if (/^Index\s+v-sweep\s+\@.*\[(.+)\]/i) {$inResults=1;$pin="OP($1)";<SIMULATE>;next} |
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@Field=split; |
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if ($#Field != 2) {$inResults=0} |
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next if (!$inResults); |
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@ -402,7 +409,9 @@ sub runDcTest { |
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} |
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printf OF ("V($main::biasSweepPin)"); |
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foreach $pin (@main::Outputs) { |
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if ($main::isFloatingPin{$pin}) { |
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if ($pin =~ /^OP/) { |
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printf OF " $pin"; |
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} elsif ($main::isFloatingPin{$pin}) { |
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printf OF (" V($pin)"); |
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} else { |
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printf OF (" I($pin)"); |
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@ -434,8 +443,18 @@ sub runDcTest { |
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sub generateCommonNetlistInfo { |
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my($variant,$temperature)=@_; |
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my(@Pin_x,$arg,$name,$value,$eFactor,$fFactor,$pin); |
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if (!defined($main::keyLetter)) { |
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if (defined($main::verilogaFile)) { |
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$main::keyLetter="N"; |
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} else { |
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die("ERROR: no keyLetter specified, stopped"); |
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} |
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} |
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foreach $pin (@main::Pin) {push(@Pin_x,"${pin}_x")} |
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print OF ".options temp=$temperature gmin=1e-13 abstol=1e-13 reltol=1e-3"; |
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# print OF ".options temp=$temperature gmin=1e-3 abstol=1e-12 reltol=1e-6"; |
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print OF ".options temp=$temperature abstol=1e-15 reltol=1e-5"; |
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print OF ".option numdgt=8"; |
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# print OF ".options temp=$temperature"; |
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if ($variant=~/^scale$/) { |
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die("ERROR: there is no scale or shrink option for ngspice, stopped"); |
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} |
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@ -454,8 +473,25 @@ sub generateCommonNetlistInfo { |
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$fFactor/=$main::mFactor; |
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} |
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} |
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my $opvars=""; |
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foreach $pin (@main::Outputs) { |
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if ($pin =~ /^OP\((.*)\)/) { |
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$opvars .= " \@${main::keyLetter}.x1.${main::keyLetter}1[$1]"; |
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} |
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} |
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if (defined($main::verilogaFile)) { |
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die("ERROR: Verilog-A model support is not implemented for ngspice, stopped"); |
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my $osdifile = $main::verilogaFile; |
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$osdifile =~ s/\.va$/\.osdi/; |
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print OF ".control"; |
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print OF "pre_osdi $osdifile"; |
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if ($opvars ne "") { |
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print OF "save $opvars"; |
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} |
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print OF ".endc"; |
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} elsif ($opvars ne "") { |
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print OF ".control"; |
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print OF "save $opvars"; |
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print OF ".endc"; |
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} |
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print OF ".subckt mysub ".join(" ",@Pin_x); |
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foreach $pin (@main::Pin) { |
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@ -491,8 +527,12 @@ sub generateCommonNetlistInfo { |
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print OF "+ $name=$value"; |
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} |
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if ($variant eq "m") { |
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if (defined($main::verilogaFile)) { |
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print OF "+ \$mfactor=$main::mFactor"; |
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} else { |
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print OF "+ m=$main::mFactor"; |
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} |
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} |
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if ($variant=~/_P/) { |
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print OF ".model mymodel $main::pTypeSelectionArguments"; |
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} else { |
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@ -505,3 +545,4 @@ sub generateCommonNetlistInfo { |
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} |
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1; |
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dwarning
2 years ago
Holger Vogt