Corrected entries as asked by Dietmar Warning.

DEVICES

@@ -321,9 +321,9 @@ VBIC	- Bipolar Junction Transistor
         Status:
  
         This is the Vertical Bipolar InterCompany model.
-	The author of VBIC is Colin McAndrew <mcandrew@ieee.org
+        The author of VBIC is Colin McAndrew mcandrew@ieee.org
         Spice3 Implementation: Dietmar Warning DAnalyse GmbH 
-	                       <warning@danalyse.de
+                               warning@danalyse.de
         Web Site:
         http://www.designers-guide.com/VBIC/index.html
         
@@ -562,13 +562,13 @@ BSIM3v0 - BSIM model level 3
  
 BSIM3v1 - BSIM model level 3
         Initial Release.
-	Ver:    3.1
+        Ver:    3.0
         Class:  M
         Level:  48
         Dir:    devices/bsim3v1a
         Status: TO BE TESTED AND IMPROVED
          
-	This is the BSIM3v3.1 model modified by Alan Gillespie. 
+        This is the BSIM3v3.0 model modified by Alan Gillespie. 
  
  
 BSIM3v1 - BSIM model level 3
@@ -584,27 +584,11 @@ BSIM3v1	- BSIM model level 3
         "HDIF" and "M" parameters.
          
  
-BSIM3v2 - BSIM model level 3
-	Initial Relese.
-	Ver:    3.2
-	Class:  M
-	Level:  50
-	Dir:    devices/bsim3v2
-	Status: TO BE TESTED
- 
-	This is the BSIM3v3.2 model. It is included only for compatibility
-	with existing netlists and parameters files. As always, tests
-	are availabe on the Berkeley's device group site.
-         
-	Web site:
-	http://www-device.eecs.berkeley.edu/~bsim3
- 
- 
 BSIM3 - BSIM model level 3
         Initial Release.
         Ver:    3.2.4
         Class:  M
-	Level:  53
+        Level:  8
         Dir:    devices/bsim3
         Status: TO BE TESTED 
          
@@ -667,7 +651,7 @@ HiSIM	- Hiroshima-university STARC IGFET Model
  
 BSIM3SOI_FD     - SOI model (fully depleted devices)
                 Initial Release.
-		Ver:    2.1. 
+                Ver:    2.1 
                 Class:  M
                 Level:  55
                 Dir:    devices/bsim3soi_fd