Netlist is flat at this stage, all numbers expanded,
but not yet parsed into the circuit structure.
So again try to remove unused MOS models.
All binning models are still here when w or l have been
determined by an expression from within the PDK.
a lot of binning models.
This is a hack and needs testing!
inpcom.c: If an x line, add w and l to the netlist card,
if available.
subckt.c: select a suitable model bin, discard the rest
for each subcircuit, depending on w and l from above.
inpgmod.c: less restrictive equal for real numbers,
allow both min and max boundaries (problem of equating
real numbers), when the selected device has w or l on
the boundary between two model bins.
Allow such strange construct, where a single pair x,y will
simplay return a constant y (120 in the above example).
This is used in external devices models and aknowledged
by other simulators.
Error message when .end card is missing
Reset if .end card is missing, to allow loading
a netlist again.
NULL as last element is no longer required, but .end card
(this has been implicitedly assumed).
Remove a bug that skippoed the last line (the .end card).
R, L, C lines invoking the B source.
Enable parameterization of the TCs.
Create a tc string in an extra function, add this string
to the new R, L, C line.
It used to contain a unused sensitivity analysis that
has not been touched for the last 15 to 20 yeras.
We are not a museum. If somebody wants to reactivate
this code, of course it is available within the older
ngspice releases.
(all *.h), nor install dlmain.c and cmpp. Nearly all
users are not interested in creating code models, it is
not documated, and a much better way to create (and test)
code models is from within the ngspice sources (as is
documented in the manual).
dwarning
Holger Vogt
Markus Mueller